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i2c-i801.c @ 4252

Revision 4252, 19.1 KB (checked in by khali, 6 years ago)
Add Intel ICH9 support.
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1	/*
2	i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware
3	monitoring
4	Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5	Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
6	<mdsxyz123@yahoo.com>
7
8	This program is free software; you can redistribute it and/or modify
9	it under the terms of the GNU General Public License as published by
10	the Free Software Foundation; either version 2 of the License, or
11	(at your option) any later version.
12
13	This program is distributed in the hope that it will be useful,
14	but WITHOUT ANY WARRANTY; without even the implied warranty of
15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	GNU General Public License for more details.
17
18	You should have received a copy of the GNU General Public License
19	along with this program; if not, write to the Free Software
20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21	*/
22
23	/*
24	SUPPORTED DEVICES PCI ID
25	82801AA 2413
26	82801AB 2423
27	82801BA 2443
28	82801CA/CAM 2483
29	82801DB 24C3 (HW PEC supported, 32 byte buffer not supported)
30	82801EB 24D3 (HW PEC supported, 32 byte buffer not supported)
31	6300ESB 25A4 ("")
32	ICH6 266A ("")
33	ICH7 27DA ("")
34	ESB2 269B ("")
35	ICH8 283E ("")
36	ICH9 2930 ("")
37
38	This driver supports several versions of Intel's I/O Controller Hubs (ICH).
39	For SMBus support, they are similar to the PIIX4 and are part
40	of Intel's '810' and other chipsets.
41	See the doc/busses/i2c-i801 file for details.
42	I2C Block Read supported for ICH5 and higher.
43	Block Process Call are not supported.
44	*/
45
46	/* Note: we assume there can only be one I801, with one SMBus interface */
47
48	/* #define DEBUG 1 */
49
50	#include <linux/module.h>
51	#include <linux/pci.h>
52	#include <linux/kernel.h>
53	#include <linux/stddef.h>
54	#include <linux/sched.h>
55	#include <linux/ioport.h>
56	#include <linux/init.h>
57	#include <linux/i2c.h>
58	#include <asm/io.h>
59	#include "version.h"
60	#include "sensors_compat.h"
61
62	/* 82801CA is undefined before kernel 2.4.13 */
63	#ifndef PCI_DEVICE_ID_INTEL_82801CA_3
64	#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483
65	#endif
66
67	/* 82801DB is undefined before kernel 2.4.19 */
68	#ifndef PCI_DEVICE_ID_INTEL_82801DB_3
69	#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3
70	#endif
71
72	/* 82801EB is undefined before kernel 2.4.21 */
73	#ifndef PCI_DEVICE_ID_INTEL_82801EB_3
74	#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3
75	#endif
76
77	/* ESB is undefined before kernel 2.4.22 */
78	#ifndef PCI_DEVICE_ID_INTEL_ESB_4
79	#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4
80	#endif
81
82	/* ESB2 - Enterprise Southbridge is undefined */
83	#ifndef PCI_DEVICE_ID_INTEL_ESB2_17
84	#define PCI_DEVICE_ID_INTEL_ESB2_17 0x269b
85	#endif
86
87	/* ICH6 is undefined */
88	#ifndef PCI_DEVICE_ID_INTEL_ICH6_16
89	#define PCI_DEVICE_ID_INTEL_ICH6_16 0x266a
90	#endif
91
92	/* ICH7 is undefined */
93	#ifndef PCI_DEVICE_ID_INTEL_ICH7_17
94	#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da
95	#endif
96
97	/* ICH8 is undefined */
98	#ifndef PCI_DEVICE_ID_INTEL_ICH8_5
99	#define PCI_DEVICE_ID_INTEL_ICH8_5 0x283e
100	#endif
101
102	/* ICH9 is undefined */
103	#ifndef PCI_DEVICE_ID_INTEL_ICH9_6
104	#define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930
105	#endif
106
107	#ifdef I2C_CLIENT_PEC
108	#define HAVE_PEC
109	#endif
110
111	/* I801 SMBus address offsets */
112	#define SMBHSTSTS (0 + i801_smba)
113	#define SMBHSTCNT (2 + i801_smba)
114	#define SMBHSTCMD (3 + i801_smba)
115	#define SMBHSTADD (4 + i801_smba)
116	#define SMBHSTDAT0 (5 + i801_smba)
117	#define SMBHSTDAT1 (6 + i801_smba)
118	#define SMBBLKDAT (7 + i801_smba)
119	#define SMBPEC (8 + i801_smba) /* ICH4 only */
120	#define SMBAUXSTS (12 + i801_smba) /* ICH4 only */
121	#define SMBAUXCTL (13 + i801_smba) /* ICH4 only */
122
123	/* PCI Address Constants */
124	#define SMBBA 0x020
125	#define SMBHSTCFG 0x040
126	#define SMBREV 0x008
127
128	/* Host configuration bits for SMBHSTCFG */
129	#define SMBHSTCFG_HST_EN 1
130	#define SMBHSTCFG_SMB_SMI_EN 2
131	#define SMBHSTCFG_I2C_EN 4
132
133	/* Other settings */
134	#define MAX_TIMEOUT 100
135	#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
136
137	/* I801 command constants */
138	#define I801_QUICK 0x00
139	#define I801_BYTE 0x04
140	#define I801_BYTE_DATA 0x08
141	#define I801_WORD_DATA 0x0C
142	#define I801_PROC_CALL 0x10 /* later chips only, unimplemented */
143	#define I801_BLOCK_DATA 0x14
144	#define I801_I2C_BLOCK_DATA 0x18 /* ich4 and later */
145	#define I801_BLOCK_LAST 0x34
146	#define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */
147	#define I801_START 0x40
148	#define I801_PEC_EN 0x80 /* ich4 and later */
149
150	/* insmod parameters */
151
152	/* If force_addr is set to anything different from 0, we forcibly enable
153	the I801 at the given address. VERY DANGEROUS! */
154	static int force_addr = 0;
155	MODULE_PARM(force_addr, "i");
156	MODULE_PARM_DESC(force_addr,
157	"Forcibly enable the I801 at the given address. "
158	"EXTREMELY DANGEROUS!");
159
160	static int i801_transaction(void);
161	static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
162	int command, int hwpec);
163
164	static unsigned short i801_smba;
165	static struct pci_driver i801_driver;
166	static struct pci_dev *I801_dev;
167	static int isich4; /* is PEC supported? */
168	static int isich5; /* is i2c block read supported? */
169
170	static int __devinit i801_setup(struct pci_dev *dev)
171	{
172	unsigned char temp;
173
174	I801_dev = dev;
175	if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_3 \|\|
176	dev->device == PCI_DEVICE_ID_INTEL_82801EB_3 \|\|
177	dev->device == PCI_DEVICE_ID_INTEL_ESB_4 \|\|
178	dev->device == PCI_DEVICE_ID_INTEL_ESB2_17 \|\|
179	dev->device == PCI_DEVICE_ID_INTEL_ICH6_16 \|\|
180	dev->device == PCI_DEVICE_ID_INTEL_ICH7_17 \|\|
181	dev->device == PCI_DEVICE_ID_INTEL_ICH8_5 \|\|
182	dev->device == PCI_DEVICE_ID_INTEL_ICH9_6)
183	isich4 = 1;
184	else
185	isich4 = 0;
186	isich5 = isich4 && dev->device != PCI_DEVICE_ID_INTEL_82801DB_3;
187
188	/* Determine the address of the SMBus area */
189	if (force_addr) {
190	i801_smba = force_addr & 0xfff0;
191	} else {
192	pci_read_config_word(I801_dev, SMBBA, &i801_smba);
193	i801_smba &= 0xfff0;
194	if(i801_smba == 0) {
195	dev_err(dev, "SMB base address uninitialized "
196	"- upgrade BIOS or use force_addr=0xaddr\n");
197	return -ENODEV;
198	}
199	}
200
201	if (!request_region(i801_smba, (isich4 ? 16 : 8), i801_driver.name)) {
202	dev_err(dev, "I801_smb region 0x%x already in use!\n",
203	i801_smba);
204	return -EBUSY;
205	}
206
207	pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
208	temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
209	pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
210
211	/* If force_addr is set, we program the new address here. Just to make
212	sure, we disable the device first. */
213	if (force_addr) {
214	pci_write_config_byte(I801_dev, SMBHSTCFG,
215	temp & ~SMBHSTCFG_HST_EN);
216	pci_write_config_word(I801_dev, SMBBA, i801_smba);
217	pci_write_config_byte(I801_dev, SMBHSTCFG,
218	temp \| SMBHSTCFG_HST_EN);
219	dev_warn(dev, "WARNING: I801 SMBus interface set to "
220	"new address %04x!\n", i801_smba);
221	} else if (!(temp & SMBHSTCFG_HST_EN)) {
222	pci_write_config_byte(I801_dev, SMBHSTCFG,
223	temp \| SMBHSTCFG_HST_EN);
224	dev_warn(dev, "enabling SMBus device\n");
225	}
226
227	if (temp & SMBHSTCFG_SMB_SMI_EN)
228	dev_dbg(dev, "I801 using Interrupt SMI# for SMBus.\n");
229	else
230	dev_dbg(dev, "I801 using PCI Interrupt for SMBus.\n");
231
232	pci_read_config_byte(I801_dev, SMBREV, &temp);
233	dev_dbg(dev, "SMBREV = 0x%X\n", temp);
234	dev_dbg(dev, "I801_smba = 0x%X\n", i801_smba);
235
236	return 0;
237	}
238
239
240	static int i801_transaction(void)
241	{
242	int temp;
243	int result = 0;
244	int timeout = 0;
245
246	dev_dbg(I801_dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
247	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
248	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
249	inb_p(SMBHSTDAT1));
250
251	/* Make sure the SMBus host is ready to start transmitting */
252	/* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
253	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
254	dev_dbg(I801_dev, "SMBus busy (%02x). Resetting...\n",
255	temp);
256	outb_p(temp, SMBHSTSTS);
257	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
258	dev_dbg(I801_dev, "Failed! (%02x)\n", temp);
259	return -1;
260	} else {
261	dev_dbg(I801_dev, "Successfull!\n");
262	}
263	}
264
265	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
266
267	/* We will always wait for a fraction of a second! */
268	do {
269	i2c_delay(1);
270	temp = inb_p(SMBHSTSTS);
271	} while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
272
273	/* If the SMBus is still busy, we give up */
274	if (timeout >= MAX_TIMEOUT) {
275	dev_dbg(I801_dev, "SMBus Timeout!\n");
276	result = -1;
277	}
278
279	if (temp & 0x10) {
280	result = -1;
281	dev_dbg(I801_dev, "Error: Failed bus transaction\n");
282	}
283
284	if (temp & 0x08) {
285	result = -1;
286	dev_err(I801_dev, "Bus collision! SMBus may be locked "
287	"until next hard reset. (sorry!)\n");
288	/* Clock stops and slave is stuck in mid-transmission */
289	}
290
291	if (temp & 0x04) {
292	result = -1;
293	dev_dbg(I801_dev, "Error: no response!\n");
294	}
295
296	if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
297	outb_p(inb(SMBHSTSTS), SMBHSTSTS);
298
299	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
300	dev_dbg(I801_dev, "Failed reset at end of transaction "
301	"(%02x)\n", temp);
302	}
303	dev_dbg(I801_dev, "Transaction (post): CNT=%02x, CMD=%02x, "
304	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
305	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
306	inb_p(SMBHSTDAT1));
307	return result;
308	}
309
310	/* All-inclusive block transaction function */
311	static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
312	int command, int hwpec)
313	{
314	int i, len;
315	int smbcmd;
316	int temp;
317	int result = 0;
318	int timeout;
319	unsigned char hostc, errmask;
320
321	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
322	if (read_write == I2C_SMBUS_WRITE) {
323	/* set I2C_EN bit in configuration register */
324	pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
325	pci_write_config_byte(I801_dev, SMBHSTCFG,
326	hostc \| SMBHSTCFG_I2C_EN);
327	} else if (!isich5) {
328	dev_err(I801_dev,
329	"I2C_SMBUS_I2C_BLOCK_READ unsupported!\n");
330	return -1;
331	}
332	}
333
334	if (read_write == I2C_SMBUS_WRITE) {
335	len = data->block[0];
336	if (len < 1)
337	len = 1;
338	if (len > 32)
339	len = 32;
340	outb_p(len, SMBHSTDAT0);
341	outb_p(data->block[1], SMBBLKDAT);
342	} else {
343	len = 32; /* max for reads */
344	}
345
346	if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
347	/* set 32 byte buffer */
348	}
349
350	for (i = 1; i <= len; i++) {
351	if (i == len && read_write == I2C_SMBUS_READ)
352	smbcmd = I801_BLOCK_LAST;
353	else if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
354	read_write == I2C_SMBUS_READ)
355	smbcmd = I801_I2C_BLOCK_DATA;
356	else
357	smbcmd = I801_BLOCK_DATA;
358	outb_p(smbcmd \| ENABLE_INT9, SMBHSTCNT);
359
360	dev_dbg(I801_dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
361	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
362	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
363	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
364
365	/* Make sure the SMBus host is ready to start transmitting */
366	temp = inb_p(SMBHSTSTS);
367	if (i == 1) {
368	/* Erronenous conditions before transaction:
369	* Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
370	errmask=0x9f;
371	} else {
372	/* Erronenous conditions during transaction:
373	* Failed, Bus_Err, Dev_Err, Intr */
374	errmask=0x1e;
375	}
376	if (temp & errmask) {
377	dev_dbg(I801_dev, "SMBus busy (%02x). "
378	"Resetting...\n", temp);
379	outb_p(temp, SMBHSTSTS);
380	if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
381	dev_err(I801_dev,
382	"Reset failed! (%02x)\n", temp);
383	result = -1;
384	goto END;
385	}
386	if (i != 1) {
387	/* if die in middle of block transaction, fail */
388	result = -1;
389	goto END;
390	}
391	}
392
393	if (i == 1)
394	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
395
396	/* We will always wait for a fraction of a second! */
397	timeout = 0;
398	do {
399	i2c_delay(1);
400	temp = inb_p(SMBHSTSTS);
401	}
402	while ((!(temp & 0x80))
403	&& (timeout++ < MAX_TIMEOUT));
404
405	/* If the SMBus is still busy, we give up */
406	if (timeout >= MAX_TIMEOUT) {
407	result = -1;
408	dev_dbg(I801_dev, "SMBus Timeout!\n");
409	}
410
411	if (temp & 0x10) {
412	result = -1;
413	dev_dbg(I801_dev,
414	"Error: Failed bus transaction\n");
415	} else if (temp & 0x08) {
416	result = -1;
417	dev_err(I801_dev, "Bus collision!\n");
418	} else if (temp & 0x04) {
419	result = -1;
420	dev_dbg(I801_dev, "Error: no response!\n");
421	}
422
423	if (i == 1 && read_write == I2C_SMBUS_READ) {
424	if (command != I2C_SMBUS_I2C_BLOCK_DATA) {
425	len = inb_p(SMBHSTDAT0);
426	if (len < 1)
427	len = 1;
428	if (len > 32)
429	len = 32;
430	data->block[0] = len;
431	} else {
432	/* if slave returns < 32 bytes transaction will fail */
433	data->block[0] = 32;
434	}
435	}
436
437	/* Retrieve/store value in SMBBLKDAT */
438	if (read_write == I2C_SMBUS_READ)
439	data->block[i] = inb_p(SMBBLKDAT);
440	if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
441	outb_p(data->block[i+1], SMBBLKDAT);
442	if ((temp & 0x9e) != 0x00)
443	outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
444
445	if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
446	dev_dbg(I801_dev,
447	"Bad status (%02x) at end of transaction\n",
448	temp);
449	}
450	dev_dbg(I801_dev, "Block (post %d): CNT=%02x, CMD=%02x, "
451	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
452	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
453	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
454
455	if (result < 0)
456	goto END;
457	}
458
459	if (hwpec) {
460	/* wait for INTR bit as advised by Intel */
461	timeout = 0;
462	do {
463	i2c_delay(1);
464	temp = inb_p(SMBHSTSTS);
465	} while ((!(temp & 0x02))
466	&& (timeout++ < MAX_TIMEOUT));
467
468	if (timeout >= MAX_TIMEOUT) {
469	dev_dbg(I801_dev, "PEC Timeout!\n");
470	}
471	outb_p(temp, SMBHSTSTS);
472	}
473	result = 0;
474	END:
475	if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
476	read_write == I2C_SMBUS_WRITE) {
477	/* restore saved configuration register value */
478	pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
479	}
480	return result;
481	}
482
483	/* Return -1 on error. */
484	static s32 i801_access(struct i2c_adapter * adap, u16 addr,
485	unsigned short flags, char read_write, u8 command,
486	int size, union i2c_smbus_data * data)
487	{
488	int hwpec = 0;
489	int block = 0;
490	int ret, xact = 0;
491
492	#ifdef HAVE_PEC
493	hwpec = isich4 && (flags & I2C_CLIENT_PEC)
494	&& size != I2C_SMBUS_QUICK
495	&& size != I2C_SMBUS_I2C_BLOCK_DATA;
496	#endif
497
498	switch (size) {
499	case I2C_SMBUS_QUICK:
500	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
501	SMBHSTADD);
502	xact = I801_QUICK;
503	break;
504	case I2C_SMBUS_BYTE:
505	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
506	SMBHSTADD);
507	if (read_write == I2C_SMBUS_WRITE)
508	outb_p(command, SMBHSTCMD);
509	xact = I801_BYTE;
510	break;
511	case I2C_SMBUS_BYTE_DATA:
512	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
513	SMBHSTADD);
514	outb_p(command, SMBHSTCMD);
515	if (read_write == I2C_SMBUS_WRITE)
516	outb_p(data->byte, SMBHSTDAT0);
517	xact = I801_BYTE_DATA;
518	break;
519	case I2C_SMBUS_WORD_DATA:
520	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
521	SMBHSTADD);
522	outb_p(command, SMBHSTCMD);
523	if (read_write == I2C_SMBUS_WRITE) {
524	outb_p(data->word & 0xff, SMBHSTDAT0);
525	outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
526	}
527	xact = I801_WORD_DATA;
528	break;
529	case I2C_SMBUS_BLOCK_DATA:
530	case I2C_SMBUS_I2C_BLOCK_DATA:
531	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
532	SMBHSTADD);
533	outb_p(command, SMBHSTCMD);
534	block = 1;
535	break;
536	case I2C_SMBUS_PROC_CALL:
537	default:
538	dev_err(I801_dev, "Unsupported transaction %d\n", size);
539	return -1;
540	}
541
542	outb_p(hwpec, SMBAUXCTL); /* enable/disable hardware PEC */
543
544	if(block)
545	ret = i801_block_transaction(data, read_write, size, hwpec);
546	else {
547	outb_p(xact \| ENABLE_INT9, SMBHSTCNT);
548	ret = i801_transaction();
549	}
550
551	/* Some BIOSes don't like it when PEC is enabled at reboot or resume
552	time, so we forcibly disable it after every transaction. */
553	if (hwpec)
554	outb_p(0, SMBAUXCTL);
555
556	if(block)
557	return ret;
558	if(ret)
559	return -1;
560	if ((read_write == I2C_SMBUS_WRITE) \|\| (xact == I801_QUICK))
561	return 0;
562
563	switch (xact & 0x7f) {
564	case I801_BYTE: /* Result put in SMBHSTDAT0 */
565	case I801_BYTE_DATA:
566	data->byte = inb_p(SMBHSTDAT0);
567	break;
568	case I801_WORD_DATA:
569	data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
570	break;
571	}
572	return 0;
573	}
574
575	static void i801_inc(struct i2c_adapter *adapter)
576	{
577	#ifdef MODULE
578	MOD_INC_USE_COUNT;
579	#endif
580	}
581
582	static void i801_dec(struct i2c_adapter *adapter)
583	{
584	#ifdef MODULE
585	MOD_DEC_USE_COUNT;
586	#endif
587	}
588
589	static u32 i801_func(struct i2c_adapter *adapter)
590	{
591	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
592	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
593	I2C_FUNC_SMBUS_BLOCK_DATA \| I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
594	#ifdef HAVE_PEC
595	\| (isich4 ? I2C_FUNC_SMBUS_HWPEC_CALC : 0)
596	#endif
597	#if 0
598	\| (isich5 ? I2C_FUNC_SMBUS_READ_I2C_BLOCK
599	: 0)
600	#endif
601	;
602	}
603
604	static struct i2c_algorithm smbus_algorithm = {
605	.name = "Non-I2C SMBus adapter",
606	.id = I2C_ALGO_SMBUS,
607	.smbus_xfer = i801_access,
608	.functionality = i801_func,
609	};
610
611	static struct i2c_adapter i801_adapter = {
612	.id = I2C_ALGO_SMBUS \| I2C_HW_SMBUS_I801,
613	.algo = &smbus_algorithm,
614	.inc_use = i801_inc,
615	.dec_use = i801_dec,
616	};
617
618	static struct pci_device_id i801_ids[] __devinitdata = {
619	{
620	.vendor = PCI_VENDOR_ID_INTEL,
621	.device = PCI_DEVICE_ID_INTEL_82801AA_3,
622	.subvendor = PCI_ANY_ID,
623	.subdevice = PCI_ANY_ID,
624	},
625	{
626	.vendor = PCI_VENDOR_ID_INTEL,
627	.device = PCI_DEVICE_ID_INTEL_82801AB_3,
628	.subvendor = PCI_ANY_ID,
629	.subdevice = PCI_ANY_ID,
630	},
631	{
632	.vendor = PCI_VENDOR_ID_INTEL,
633	.device = PCI_DEVICE_ID_INTEL_82801BA_2,
634	.subvendor = PCI_ANY_ID,
635	.subdevice = PCI_ANY_ID,
636	},
637	{
638	.vendor = PCI_VENDOR_ID_INTEL,
639	.device = PCI_DEVICE_ID_INTEL_82801CA_3,
640	.subvendor = PCI_ANY_ID,
641	.subdevice = PCI_ANY_ID,
642	},
643	{
644	.vendor = PCI_VENDOR_ID_INTEL,
645	.device = PCI_DEVICE_ID_INTEL_82801DB_3,
646	.subvendor = PCI_ANY_ID,
647	.subdevice = PCI_ANY_ID,
648	},
649	{
650	.vendor = PCI_VENDOR_ID_INTEL,
651	.device = PCI_DEVICE_ID_INTEL_82801EB_3,
652	.subvendor = PCI_ANY_ID,
653	.subdevice = PCI_ANY_ID,
654	},
655	{
656	.vendor = PCI_VENDOR_ID_INTEL,
657	.device = PCI_DEVICE_ID_INTEL_ESB_4,
658	.subvendor = PCI_ANY_ID,
659	.subdevice = PCI_ANY_ID,
660	},
661	{
662	.vendor = PCI_VENDOR_ID_INTEL,
663	.device = PCI_DEVICE_ID_INTEL_ESB2_17,
664	.subvendor = PCI_ANY_ID,
665	.subdevice = PCI_ANY_ID,
666	},
667	{
668	.vendor = PCI_VENDOR_ID_INTEL,
669	.device = PCI_DEVICE_ID_INTEL_ICH6_16,
670	.subvendor = PCI_ANY_ID,
671	.subdevice = PCI_ANY_ID,
672	},
673	{
674	.vendor = PCI_VENDOR_ID_INTEL,
675	.device = PCI_DEVICE_ID_INTEL_ICH7_17,
676	.subvendor = PCI_ANY_ID,
677	.subdevice = PCI_ANY_ID,
678	},
679	{
680	.vendor = PCI_VENDOR_ID_INTEL,
681	.device = PCI_DEVICE_ID_INTEL_ICH8_5,
682	.subvendor = PCI_ANY_ID,
683	.subdevice = PCI_ANY_ID,
684	},
685	{
686	.vendor = PCI_VENDOR_ID_INTEL,
687	.device = PCI_DEVICE_ID_INTEL_ICH9_6,
688	.subvendor = PCI_ANY_ID,
689	.subdevice = PCI_ANY_ID,
690	},
691	{ 0, }
692	};
693
694	static int __devinit i801_probe(struct pci_dev dev, const struct pci_device_id id)
695	{
696	int err;
697
698	if ((err = i801_setup(dev)))
699	return err;
700
701	snprintf(i801_adapter.name, 32,
702	"SMBus I801 adapter at %04x", i801_smba);
703	return i2c_add_adapter(&i801_adapter);
704	}
705
706	static void __devexit i801_remove(struct pci_dev *dev)
707	{
708	i2c_del_adapter(&i801_adapter);
709	release_region(i801_smba, (isich4 ? 16 : 8));
710	}
711
712	static struct pci_driver i801_driver = {
713	.name = "i801 smbus",
714	.id_table = i801_ids,
715	.probe = i801_probe,
716	.remove = __devexit_p(i801_remove),
717	};
718
719	static int __init i2c_i801_init(void)
720	{
721	printk(KERN_INFO "i2c-i801 version %s (%s)\n", LM_VERSION, LM_DATE);
722	return pci_module_init(&i801_driver);
723	}
724
725	static void __exit i2c_i801_exit(void)
726	{
727	pci_unregister_driver(&i801_driver);
728	}
729
730	MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
731	"Philip Edelbrock <phil@netroedge.com>, "
732	"and Mark D. Studebaker <mdsxyz123@yahoo.com>");
733	MODULE_DESCRIPTION("I801 SMBus driver");
734	MODULE_LICENSE("GPL");
735
736	module_init(i2c_i801_init);
737	module_exit(i2c_i801_exit);

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