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i2c-i801.c @ 4060

Revision 4060, 18.8 KB (checked in by khali, 7 years ago)

i2c-i801: Remove PCI function check

Remove the PCI function number check when probing devices.
This check is redundant, each function has a separate PCI device
ID, so checking for that ID is sufficient.

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1	/*
2	i801.c - Part of lm_sensors, Linux kernel modules for hardware
3	monitoring
4	Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5	Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
6	<mdsxyz123@yahoo.com>
7
8	This program is free software; you can redistribute it and/or modify
9	it under the terms of the GNU General Public License as published by
10	the Free Software Foundation; either version 2 of the License, or
11	(at your option) any later version.
12
13	This program is distributed in the hope that it will be useful,
14	but WITHOUT ANY WARRANTY; without even the implied warranty of
15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	GNU General Public License for more details.
17
18	You should have received a copy of the GNU General Public License
19	along with this program; if not, write to the Free Software
20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21	*/
22
23	/*
24	SUPPORTED DEVICES PCI ID
25	82801AA 2413
26	82801AB 2423
27	82801BA 2443
28	82801CA/CAM 2483
29	82801DB 24C3 (HW PEC supported, 32 byte buffer not supported)
30	82801EB 24D3 (HW PEC supported, 32 byte buffer not supported)
31	6300ESB 25A4 ("")
32	ICH6 266A ("")
33	ICH7 27DA ("")
34	ESB2 269B ("")
35	ICH8 283E ("")
36
37	This driver supports several versions of Intel's I/O Controller Hubs (ICH).
38	For SMBus support, they are similar to the PIIX4 and are part
39	of Intel's '810' and other chipsets.
40	See the doc/busses/i2c-i801 file for details.
41	I2C Block Read supported for ICH5 and higher.
42	Block Process Call are not supported.
43	*/
44
45	/* Note: we assume there can only be one I801, with one SMBus interface */
46
47	/* #define DEBUG 1 */
48
49	#include <linux/module.h>
50	#include <linux/pci.h>
51	#include <linux/kernel.h>
52	#include <linux/stddef.h>
53	#include <linux/sched.h>
54	#include <linux/ioport.h>
55	#include <linux/init.h>
56	#include <linux/i2c.h>
57	#include <asm/io.h>
58	#include "version.h"
59	#include "sensors_compat.h"
60
61	/* 82801CA is undefined before kernel 2.4.13 */
62	#ifndef PCI_DEVICE_ID_INTEL_82801CA_3
63	#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483
64	#endif
65
66	/* 82801DB is undefined before kernel 2.4.19 */
67	#ifndef PCI_DEVICE_ID_INTEL_82801DB_3
68	#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3
69	#endif
70
71	/* 82801EB is undefined before kernel 2.4.21 */
72	#ifndef PCI_DEVICE_ID_INTEL_82801EB_3
73	#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3
74	#endif
75
76	/* ESB is undefined before kernel 2.4.22 */
77	#ifndef PCI_DEVICE_ID_INTEL_ESB_4
78	#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4
79	#endif
80
81	/* ESB2 - Enterprise Southbridge is undefined */
82	#ifndef PCI_DEVICE_ID_INTEL_ESB2_17
83	#define PCI_DEVICE_ID_INTEL_ESB2_17 0x269b
84	#endif
85
86	/* ICH6 is undefined */
87	#ifndef PCI_DEVICE_ID_INTEL_ICH6_16
88	#define PCI_DEVICE_ID_INTEL_ICH6_16 0x266a
89	#endif
90
91	/* ICH7 is undefined */
92	#ifndef PCI_DEVICE_ID_INTEL_ICH7_17
93	#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da
94	#endif
95
96	/* ICH8 is undefined */
97	#ifndef PCI_DEVICE_ID_INTEL_ICH8_5
98	#define PCI_DEVICE_ID_INTEL_ICH8_5 0x283e
99	#endif
100
101	#ifdef I2C_CLIENT_PEC
102	#define HAVE_PEC
103	#endif
104
105	/* I801 SMBus address offsets */
106	#define SMBHSTSTS (0 + i801_smba)
107	#define SMBHSTCNT (2 + i801_smba)
108	#define SMBHSTCMD (3 + i801_smba)
109	#define SMBHSTADD (4 + i801_smba)
110	#define SMBHSTDAT0 (5 + i801_smba)
111	#define SMBHSTDAT1 (6 + i801_smba)
112	#define SMBBLKDAT (7 + i801_smba)
113	#define SMBPEC (8 + i801_smba) /* ICH4 only */
114	#define SMBAUXSTS (12 + i801_smba) /* ICH4 only */
115	#define SMBAUXCTL (13 + i801_smba) /* ICH4 only */
116
117	/* PCI Address Constants */
118	#define SMBBA 0x020
119	#define SMBHSTCFG 0x040
120	#define SMBREV 0x008
121
122	/* Host configuration bits for SMBHSTCFG */
123	#define SMBHSTCFG_HST_EN 1
124	#define SMBHSTCFG_SMB_SMI_EN 2
125	#define SMBHSTCFG_I2C_EN 4
126
127	/* Other settings */
128	#define MAX_TIMEOUT 100
129	#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
130
131	/* I801 command constants */
132	#define I801_QUICK 0x00
133	#define I801_BYTE 0x04
134	#define I801_BYTE_DATA 0x08
135	#define I801_WORD_DATA 0x0C
136	#define I801_PROC_CALL 0x10 /* later chips only, unimplemented */
137	#define I801_BLOCK_DATA 0x14
138	#define I801_I2C_BLOCK_DATA 0x18 /* ich4 and later */
139	#define I801_BLOCK_LAST 0x34
140	#define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */
141	#define I801_START 0x40
142	#define I801_PEC_EN 0x80 /* ich4 and later */
143
144	/* insmod parameters */
145
146	/* If force_addr is set to anything different from 0, we forcibly enable
147	the I801 at the given address. VERY DANGEROUS! */
148	static int force_addr = 0;
149	MODULE_PARM(force_addr, "i");
150	MODULE_PARM_DESC(force_addr,
151	"Forcibly enable the I801 at the given address. "
152	"EXTREMELY DANGEROUS!");
153
154	static int i801_transaction(void);
155	static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
156	int command, int hwpec);
157
158	static unsigned short i801_smba;
159	static struct pci_driver i801_driver;
160	static struct pci_dev *I801_dev;
161	static int isich4; /* is PEC supported? */
162	static int isich5; /* is i2c block read supported? */
163
164	static int i801_setup(struct pci_dev *dev)
165	{
166	int error_return = 0;
167	unsigned char temp;
168
169	I801_dev = dev;
170	if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_3 \|\|
171	dev->device == PCI_DEVICE_ID_INTEL_82801EB_3 \|\|
172	dev->device == PCI_DEVICE_ID_INTEL_ESB_4 \|\|
173	dev->device == PCI_DEVICE_ID_INTEL_ESB2_17 \|\|
174	dev->device == PCI_DEVICE_ID_INTEL_ICH6_16 \|\|
175	dev->device == PCI_DEVICE_ID_INTEL_ICH7_17 \|\|
176	dev->device == PCI_DEVICE_ID_INTEL_ICH8_5)
177	isich4 = 1;
178	else
179	isich4 = 0;
180	isich5 = isich4 && dev->device != PCI_DEVICE_ID_INTEL_82801DB_3;
181
182	/* Determine the address of the SMBus areas */
183	if (force_addr) {
184	i801_smba = force_addr & 0xfff0;
185	} else {
186	pci_read_config_word(I801_dev, SMBBA, &i801_smba);
187	i801_smba &= 0xfff0;
188	if(i801_smba == 0) {
189	dev_err(dev, "SMB base address uninitialized "
190	"- upgrade BIOS or use force_addr=0xaddr\n");
191	return -ENODEV;
192	}
193	}
194
195	if (!request_region(i801_smba, (isich4 ? 16 : 8), i801_driver.name)) {
196	dev_err(dev, "I801_smb region 0x%x already in use!\n",
197	i801_smba);
198	error_return = -EBUSY;
199	goto END;
200	}
201
202	pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
203	temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
204	pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
205
206	/* If force_addr is set, we program the new address here. Just to make
207	sure, we disable the device first. */
208	if (force_addr) {
209	pci_write_config_byte(I801_dev, SMBHSTCFG, temp & 0xfe);
210	pci_write_config_word(I801_dev, SMBBA, i801_smba);
211	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 0x01);
212	dev_warn(dev, "WARNING: I801 SMBus interface set to "
213	"new address %04x!\n", i801_smba);
214	} else if ((temp & 1) == 0) {
215	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 1);
216	dev_warn(dev, "enabling SMBus device\n");
217	}
218
219	if (temp & 0x02)
220	dev_dbg(dev, "I801 using Interrupt SMI# for SMBus.\n");
221	else
222	dev_dbg(dev, "I801 using PCI Interrupt for SMBus.\n");
223
224	pci_read_config_byte(I801_dev, SMBREV, &temp);
225	dev_dbg(dev, "SMBREV = 0x%X\n", temp);
226	dev_dbg(dev, "I801_smba = 0x%X\n", i801_smba);
227
228	END:
229	return error_return;
230	}
231
232
233	static int i801_transaction(void)
234	{
235	int temp;
236	int result = 0;
237	int timeout = 0;
238
239	dev_dbg(I801_dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
240	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
241	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
242	inb_p(SMBHSTDAT1));
243
244	/* Make sure the SMBus host is ready to start transmitting */
245	/* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
246	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
247	dev_dbg(I801_dev, "SMBus busy (%02x). Resetting...\n",
248	temp);
249	outb_p(temp, SMBHSTSTS);
250	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
251	dev_dbg(I801_dev, "Failed! (%02x)\n", temp);
252	return -1;
253	} else {
254	dev_dbg(I801_dev, "Successfull!\n");
255	}
256	}
257
258	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
259
260	/* We will always wait for a fraction of a second! */
261	do {
262	i2c_delay(1);
263	temp = inb_p(SMBHSTSTS);
264	} while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
265
266	/* If the SMBus is still busy, we give up */
267	if (timeout >= MAX_TIMEOUT) {
268	dev_dbg(I801_dev, "SMBus Timeout!\n");
269	result = -1;
270	}
271
272	if (temp & 0x10) {
273	result = -1;
274	dev_dbg(I801_dev, "Error: Failed bus transaction\n");
275	}
276
277	if (temp & 0x08) {
278	result = -1;
279	dev_err(I801_dev, "Bus collision! SMBus may be locked "
280	"until next hard reset. (sorry!)\n");
281	/* Clock stops and slave is stuck in mid-transmission */
282	}
283
284	if (temp & 0x04) {
285	result = -1;
286	dev_dbg(I801_dev, "Error: no response!\n");
287	}
288
289	if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
290	outb_p(inb(SMBHSTSTS), SMBHSTSTS);
291
292	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
293	dev_dbg(I801_dev, "Failed reset at end of transaction "
294	"(%02x)\n", temp);
295	}
296	dev_dbg(I801_dev, "Transaction (post): CNT=%02x, CMD=%02x, "
297	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
298	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
299	inb_p(SMBHSTDAT1));
300	return result;
301	}
302
303	/* All-inclusive block transaction function */
304	static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
305	int command, int hwpec)
306	{
307	int i, len;
308	int smbcmd;
309	int temp;
310	int result = 0;
311	int timeout;
312	unsigned char hostc, errmask;
313
314	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
315	if (read_write == I2C_SMBUS_WRITE) {
316	/* set I2C_EN bit in configuration register */
317	pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
318	pci_write_config_byte(I801_dev, SMBHSTCFG,
319	hostc \| SMBHSTCFG_I2C_EN);
320	} else if (!isich5) {
321	dev_err(I801_dev,
322	"I2C_SMBUS_I2C_BLOCK_READ unsupported!\n");
323	return -1;
324	}
325	}
326
327	if (read_write == I2C_SMBUS_WRITE) {
328	len = data->block[0];
329	if (len < 1)
330	len = 1;
331	if (len > 32)
332	len = 32;
333	outb_p(len, SMBHSTDAT0);
334	outb_p(data->block[1], SMBBLKDAT);
335	} else {
336	len = 32; /* max for reads */
337	}
338
339	if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
340	/* set 32 byte buffer */
341	}
342
343	for (i = 1; i <= len; i++) {
344	if (i == len && read_write == I2C_SMBUS_READ)
345	smbcmd = I801_BLOCK_LAST;
346	else if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
347	read_write == I2C_SMBUS_READ)
348	smbcmd = I801_I2C_BLOCK_DATA;
349	else
350	smbcmd = I801_BLOCK_DATA;
351	outb_p(smbcmd \| ENABLE_INT9, SMBHSTCNT);
352
353	dev_dbg(I801_dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
354	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
355	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
356	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
357
358	/* Make sure the SMBus host is ready to start transmitting */
359	temp = inb_p(SMBHSTSTS);
360	if (i == 1) {
361	/* Erronenous conditions before transaction:
362	* Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
363	errmask=0x9f;
364	} else {
365	/* Erronenous conditions during transaction:
366	* Failed, Bus_Err, Dev_Err, Intr */
367	errmask=0x1e;
368	}
369	if (temp & errmask) {
370	dev_dbg(I801_dev, "SMBus busy (%02x). "
371	"Resetting...\n", temp);
372	outb_p(temp, SMBHSTSTS);
373	if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
374	dev_err(I801_dev,
375	"Reset failed! (%02x)\n", temp);
376	result = -1;
377	goto END;
378	}
379	if (i != 1) {
380	/* if die in middle of block transaction, fail */
381	result = -1;
382	goto END;
383	}
384	}
385
386	if (i == 1)
387	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
388
389	/* We will always wait for a fraction of a second! */
390	timeout = 0;
391	do {
392	i2c_delay(1);
393	temp = inb_p(SMBHSTSTS);
394	}
395	while ((!(temp & 0x80))
396	&& (timeout++ < MAX_TIMEOUT));
397
398	/* If the SMBus is still busy, we give up */
399	if (timeout >= MAX_TIMEOUT) {
400	result = -1;
401	dev_dbg(I801_dev, "SMBus Timeout!\n");
402	}
403
404	if (temp & 0x10) {
405	result = -1;
406	dev_dbg(I801_dev,
407	"Error: Failed bus transaction\n");
408	} else if (temp & 0x08) {
409	result = -1;
410	dev_err(I801_dev, "Bus collision!\n");
411	} else if (temp & 0x04) {
412	result = -1;
413	dev_dbg(I801_dev, "Error: no response!\n");
414	}
415
416	if (i == 1 && read_write == I2C_SMBUS_READ) {
417	if (command != I2C_SMBUS_I2C_BLOCK_DATA) {
418	len = inb_p(SMBHSTDAT0);
419	if (len < 1)
420	len = 1;
421	if (len > 32)
422	len = 32;
423	data->block[0] = len;
424	} else {
425	/* if slave returns < 32 bytes transaction will fail */
426	data->block[0] = 32;
427	}
428	}
429
430	/* Retrieve/store value in SMBBLKDAT */
431	if (read_write == I2C_SMBUS_READ)
432	data->block[i] = inb_p(SMBBLKDAT);
433	if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
434	outb_p(data->block[i+1], SMBBLKDAT);
435	if ((temp & 0x9e) != 0x00)
436	outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
437
438	if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
439	dev_dbg(I801_dev,
440	"Bad status (%02x) at end of transaction\n",
441	temp);
442	}
443	dev_dbg(I801_dev, "Block (post %d): CNT=%02x, CMD=%02x, "
444	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
445	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
446	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
447
448	if (result < 0)
449	goto END;
450	}
451
452	if (hwpec) {
453	/* wait for INTR bit as advised by Intel */
454	timeout = 0;
455	do {
456	i2c_delay(1);
457	temp = inb_p(SMBHSTSTS);
458	} while ((!(temp & 0x02))
459	&& (timeout++ < MAX_TIMEOUT));
460
461	if (timeout >= MAX_TIMEOUT) {
462	dev_dbg(I801_dev, "PEC Timeout!\n");
463	}
464	outb_p(temp, SMBHSTSTS);
465	}
466	result = 0;
467	END:
468	if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
469	read_write == I2C_SMBUS_WRITE) {
470	/* restore saved configuration register value */
471	pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
472	}
473	return result;
474	}
475
476	/* Return -1 on error. */
477	static s32 i801_access(struct i2c_adapter * adap, u16 addr,
478	unsigned short flags, char read_write, u8 command,
479	int size, union i2c_smbus_data * data)
480	{
481	int hwpec = 0;
482	int block = 0;
483	int ret, xact = 0;
484
485	#ifdef HAVE_PEC
486	hwpec = isich4 && (flags & I2C_CLIENT_PEC)
487	&& size != I2C_SMBUS_QUICK
488	&& size != I2C_SMBUS_I2C_BLOCK_DATA;
489	#endif
490
491	switch (size) {
492	case I2C_SMBUS_QUICK:
493	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
494	SMBHSTADD);
495	xact = I801_QUICK;
496	break;
497	case I2C_SMBUS_BYTE:
498	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
499	SMBHSTADD);
500	if (read_write == I2C_SMBUS_WRITE)
501	outb_p(command, SMBHSTCMD);
502	xact = I801_BYTE;
503	break;
504	case I2C_SMBUS_BYTE_DATA:
505	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
506	SMBHSTADD);
507	outb_p(command, SMBHSTCMD);
508	if (read_write == I2C_SMBUS_WRITE)
509	outb_p(data->byte, SMBHSTDAT0);
510	xact = I801_BYTE_DATA;
511	break;
512	case I2C_SMBUS_WORD_DATA:
513	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
514	SMBHSTADD);
515	outb_p(command, SMBHSTCMD);
516	if (read_write == I2C_SMBUS_WRITE) {
517	outb_p(data->word & 0xff, SMBHSTDAT0);
518	outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
519	}
520	xact = I801_WORD_DATA;
521	break;
522	case I2C_SMBUS_BLOCK_DATA:
523	case I2C_SMBUS_I2C_BLOCK_DATA:
524	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
525	SMBHSTADD);
526	outb_p(command, SMBHSTCMD);
527	block = 1;
528	break;
529	case I2C_SMBUS_PROC_CALL:
530	default:
531	dev_err(I801_dev, "Unsupported transaction %d\n", size);
532	return -1;
533	}
534
535	outb_p(hwpec, SMBAUXCTL); /* enable/disable hardware PEC */
536
537	if(block)
538	ret = i801_block_transaction(data, read_write, size, hwpec);
539	else {
540	outb_p(xact \| ENABLE_INT9, SMBHSTCNT);
541	ret = i801_transaction();
542	}
543
544	/* Some BIOSes don't like it when PEC is enabled at reboot or resume
545	time, so we forcibly disable it after every transaction. */
546	if (hwpec)
547	outb_p(0, SMBAUXCTL);
548
549	if(block)
550	return ret;
551	if(ret)
552	return -1;
553	if ((read_write == I2C_SMBUS_WRITE) \|\| (xact == I801_QUICK))
554	return 0;
555
556	switch (xact & 0x7f) {
557	case I801_BYTE: /* Result put in SMBHSTDAT0 */
558	case I801_BYTE_DATA:
559	data->byte = inb_p(SMBHSTDAT0);
560	break;
561	case I801_WORD_DATA:
562	data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
563	break;
564	}
565	return 0;
566	}
567
568	static void i801_inc(struct i2c_adapter *adapter)
569	{
570	#ifdef MODULE
571	MOD_INC_USE_COUNT;
572	#endif
573	}
574
575	static void i801_dec(struct i2c_adapter *adapter)
576	{
577	#ifdef MODULE
578	MOD_DEC_USE_COUNT;
579	#endif
580	}
581
582	static u32 i801_func(struct i2c_adapter *adapter)
583	{
584	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
585	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
586	I2C_FUNC_SMBUS_BLOCK_DATA \| I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
587	#ifdef HAVE_PEC
588	\| (isich4 ? I2C_FUNC_SMBUS_HWPEC_CALC : 0)
589	#endif
590	#if 0
591	\| (isich5 ? I2C_FUNC_SMBUS_READ_I2C_BLOCK
592	: 0)
593	#endif
594	;
595	}
596
597	static struct i2c_algorithm smbus_algorithm = {
598	.name = "Non-I2C SMBus adapter",
599	.id = I2C_ALGO_SMBUS,
600	.smbus_xfer = i801_access,
601	.functionality = i801_func,
602	};
603
604	static struct i2c_adapter i801_adapter = {
605	.id = I2C_ALGO_SMBUS \| I2C_HW_SMBUS_I801,
606	.algo = &smbus_algorithm,
607	.inc_use = i801_inc,
608	.dec_use = i801_dec,
609	};
610
611	static struct pci_device_id i801_ids[] __devinitdata = {
612	{
613	.vendor = PCI_VENDOR_ID_INTEL,
614	.device = PCI_DEVICE_ID_INTEL_82801AA_3,
615	.subvendor = PCI_ANY_ID,
616	.subdevice = PCI_ANY_ID,
617	},
618	{
619	.vendor = PCI_VENDOR_ID_INTEL,
620	.device = PCI_DEVICE_ID_INTEL_82801AB_3,
621	.subvendor = PCI_ANY_ID,
622	.subdevice = PCI_ANY_ID,
623	},
624	{
625	.vendor = PCI_VENDOR_ID_INTEL,
626	.device = PCI_DEVICE_ID_INTEL_82801BA_2,
627	.subvendor = PCI_ANY_ID,
628	.subdevice = PCI_ANY_ID,
629	},
630	{
631	.vendor = PCI_VENDOR_ID_INTEL,
632	.device = PCI_DEVICE_ID_INTEL_82801CA_3,
633	.subvendor = PCI_ANY_ID,
634	.subdevice = PCI_ANY_ID,
635	},
636	{
637	.vendor = PCI_VENDOR_ID_INTEL,
638	.device = PCI_DEVICE_ID_INTEL_82801DB_3,
639	.subvendor = PCI_ANY_ID,
640	.subdevice = PCI_ANY_ID,
641	},
642	{
643	.vendor = PCI_VENDOR_ID_INTEL,
644	.device = PCI_DEVICE_ID_INTEL_82801EB_3,
645	.subvendor = PCI_ANY_ID,
646	.subdevice = PCI_ANY_ID,
647	},
648	{
649	.vendor = PCI_VENDOR_ID_INTEL,
650	.device = PCI_DEVICE_ID_INTEL_ESB_4,
651	.subvendor = PCI_ANY_ID,
652	.subdevice = PCI_ANY_ID,
653	},
654	{
655	.vendor = PCI_VENDOR_ID_INTEL,
656	.device = PCI_DEVICE_ID_INTEL_ESB2_17,
657	.subvendor = PCI_ANY_ID,
658	.subdevice = PCI_ANY_ID,
659	},
660	{
661	.vendor = PCI_VENDOR_ID_INTEL,
662	.device = PCI_DEVICE_ID_INTEL_ICH6_16,
663	.subvendor = PCI_ANY_ID,
664	.subdevice = PCI_ANY_ID,
665	},
666	{
667	.vendor = PCI_VENDOR_ID_INTEL,
668	.device = PCI_DEVICE_ID_INTEL_ICH7_17,
669	.subvendor = PCI_ANY_ID,
670	.subdevice = PCI_ANY_ID,
671	},
672	{
673	.vendor = PCI_VENDOR_ID_INTEL,
674	.device = PCI_DEVICE_ID_INTEL_ICH8_5,
675	.subvendor = PCI_ANY_ID,
676	.subdevice = PCI_ANY_ID,
677	},
678	{ 0, }
679	};
680
681	static int __devinit i801_probe(struct pci_dev dev, const struct pci_device_id id)
682	{
683
684	if (i801_setup(dev)) {
685	dev_warn(dev,
686	"I801 not detected, module not inserted.\n");
687	return -ENODEV;
688	}
689
690	snprintf(i801_adapter.name, 32,
691	"SMBus I801 adapter at %04x", i801_smba);
692	return i2c_add_adapter(&i801_adapter);
693	}
694
695	static void __devexit i801_remove(struct pci_dev *dev)
696	{
697	i2c_del_adapter(&i801_adapter);
698	release_region(i801_smba, (isich4 ? 16 : 8));
699	}
700
701	static struct pci_driver i801_driver = {
702	.name = "i801 smbus",
703	.id_table = i801_ids,
704	.probe = i801_probe,
705	.remove = __devexit_p(i801_remove),
706	};
707
708	static int __init i2c_i801_init(void)
709	{
710	printk(KERN_INFO "i2c-i801 version %s (%s)\n", LM_VERSION, LM_DATE);
711	return pci_module_init(&i801_driver);
712	}
713
714	static void __exit i2c_i801_exit(void)
715	{
716	pci_unregister_driver(&i801_driver);
717	}
718
719	MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
720	"Philip Edelbrock <phil@netroedge.com>, "
721	"and Mark D. Studebaker <mdsxyz123@yahoo.com>");
722	MODULE_DESCRIPTION("I801 SMBus driver");
723	MODULE_LICENSE("GPL");
724
725	module_init(i2c_i801_init);
726	module_exit(i2c_i801_exit);

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