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i2c-i801.c @ 3176

Revision 3176, 18.8 KB (checked in by khali, 8 years ago)

Backport SMBus PEC support rewrite from Linux 2.6:

Discard I2C_FUNC_SMBUS_*_PEC defines. i2c clients are not supposed to
check for PEC support of i2c bus drivers on individual SMBus
transactions, and i2c bus drivers are not supposed to advertise them.

Property svn:eol-style set to native
Property svn:keywords set to Author Date Id Revision

Line
1	/*
2	i801.c - Part of lm_sensors, Linux kernel modules for hardware
3	monitoring
4	Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5	Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
6	<mdsxyz123@yahoo.com>
7
8	This program is free software; you can redistribute it and/or modify
9	it under the terms of the GNU General Public License as published by
10	the Free Software Foundation; either version 2 of the License, or
11	(at your option) any later version.
12
13	This program is distributed in the hope that it will be useful,
14	but WITHOUT ANY WARRANTY; without even the implied warranty of
15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	GNU General Public License for more details.
17
18	You should have received a copy of the GNU General Public License
19	along with this program; if not, write to the Free Software
20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21	*/
22
23	/*
24	SUPPORTED DEVICES PCI ID
25	82801AA 2413
26	82801AB 2423
27	82801BA 2443
28	82801CA/CAM 2483
29	82801DB 24C3 (HW PEC supported, 32 byte buffer not supported)
30	82801EB 24D3 (HW PEC supported, 32 byte buffer not supported)
31	6300ESB 25A4 ("")
32	ICH6 266A ("")
33	ICH7 27DA ("")
34	ESB2 269B ("")
35	This driver supports several versions of Intel's I/O Controller Hubs (ICH).
36	For SMBus support, they are similar to the PIIX4 and are part
37	of Intel's '810' and other chipsets.
38	See the doc/busses/i2c-i801 file for details.
39	I2C Block Read supported for ICH5 and higher.
40	Block Process Call are not supported.
41	*/
42
43	/* Note: we assume there can only be one I801, with one SMBus interface */
44
45	/* #define DEBUG 1 */
46
47	#include <linux/module.h>
48	#include <linux/pci.h>
49	#include <linux/kernel.h>
50	#include <linux/stddef.h>
51	#include <linux/sched.h>
52	#include <linux/ioport.h>
53	#include <linux/init.h>
54	#include <linux/i2c.h>
55	#include <asm/io.h>
56	#include "version.h"
57	#include "sensors_compat.h"
58
59	/* 82801CA is undefined before kernel 2.4.13 */
60	#ifndef PCI_DEVICE_ID_INTEL_82801CA_3
61	#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483
62	#endif
63
64	/* 82801DB is undefined before kernel 2.4.19 */
65	#ifndef PCI_DEVICE_ID_INTEL_82801DB_3
66	#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3
67	#endif
68
69	/* 82801EB is undefined before kernel 2.4.21 */
70	#ifndef PCI_DEVICE_ID_INTEL_82801EB_3
71	#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3
72	#endif
73
74	/* ESB is undefined before kernel 2.4.22 */
75	#ifndef PCI_DEVICE_ID_INTEL_ESB_4
76	#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4
77	#endif
78
79	/* ESB2 - Enterprise Southbridge is undefined */
80	#ifndef PCI_DEVICE_ID_INTEL_ESB2_17
81	#define PCI_DEVICE_ID_INTEL_ESB2_17 0x269b
82	#endif
83
84	/* ICH6 is undefined */
85	#ifndef PCI_DEVICE_ID_INTEL_ICH6_16
86	#define PCI_DEVICE_ID_INTEL_ICH6_16 0x266a
87	#endif
88
89	/* ICH7 is undefined */
90	#ifndef PCI_DEVICE_ID_INTEL_ICH7_17
91	#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da
92	#endif
93
94	#ifdef I2C_CLIENT_PEC
95	#define HAVE_PEC
96	#endif
97
98	/* I801 SMBus address offsets */
99	#define SMBHSTSTS (0 + i801_smba)
100	#define SMBHSTCNT (2 + i801_smba)
101	#define SMBHSTCMD (3 + i801_smba)
102	#define SMBHSTADD (4 + i801_smba)
103	#define SMBHSTDAT0 (5 + i801_smba)
104	#define SMBHSTDAT1 (6 + i801_smba)
105	#define SMBBLKDAT (7 + i801_smba)
106	#define SMBPEC (8 + i801_smba) /* ICH4 only */
107	#define SMBAUXSTS (12 + i801_smba) /* ICH4 only */
108	#define SMBAUXCTL (13 + i801_smba) /* ICH4 only */
109
110	/* PCI Address Constants */
111	#define SMBBA 0x020
112	#define SMBHSTCFG 0x040
113	#define SMBREV 0x008
114
115	/* Host configuration bits for SMBHSTCFG */
116	#define SMBHSTCFG_HST_EN 1
117	#define SMBHSTCFG_SMB_SMI_EN 2
118	#define SMBHSTCFG_I2C_EN 4
119
120	/* Other settings */
121	#define MAX_TIMEOUT 100
122	#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
123
124	/* I801 command constants */
125	#define I801_QUICK 0x00
126	#define I801_BYTE 0x04
127	#define I801_BYTE_DATA 0x08
128	#define I801_WORD_DATA 0x0C
129	#define I801_PROC_CALL 0x10 /* later chips only, unimplemented */
130	#define I801_BLOCK_DATA 0x14
131	#define I801_I2C_BLOCK_DATA 0x18 /* ich4 and later */
132	#define I801_BLOCK_LAST 0x34
133	#define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */
134	#define I801_START 0x40
135	#define I801_PEC_EN 0x80 /* ich4 and later */
136
137	/* insmod parameters */
138
139	/* If force_addr is set to anything different from 0, we forcibly enable
140	the I801 at the given address. VERY DANGEROUS! */
141	static int force_addr = 0;
142	MODULE_PARM(force_addr, "i");
143	MODULE_PARM_DESC(force_addr,
144	"Forcibly enable the I801 at the given address. "
145	"EXTREMELY DANGEROUS!");
146
147	static int i801_transaction(void);
148	static int i801_block_transaction(union i2c_smbus_data *data,
149	char read_write, int command);
150
151	static unsigned short i801_smba;
152	static struct pci_driver i801_driver;
153	static struct pci_dev *I801_dev;
154	static int isich4; /* is PEC supported? */
155	static int isich5; /* is i2c block read supported? */
156
157	static int i801_setup(struct pci_dev *dev)
158	{
159	int error_return = 0;
160	unsigned char temp;
161
162	/* Note: we keep on searching until we have found 'function 3' */
163	if(PCI_FUNC(dev->devfn) != 3)
164	return -ENODEV;
165
166	I801_dev = dev;
167	if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_3 \|\|
168	dev->device == PCI_DEVICE_ID_INTEL_82801EB_3 \|\|
169	dev->device == PCI_DEVICE_ID_INTEL_ESB_4 \|\|
170	dev->device == PCI_DEVICE_ID_INTEL_ESB2_17 \|\|
171	dev->device == PCI_DEVICE_ID_INTEL_ICH6_16 \|\|
172	dev->device == PCI_DEVICE_ID_INTEL_ICH7_17)
173	isich4 = 1;
174	else
175	isich4 = 0;
176	isich5 = isich4 && dev->device != PCI_DEVICE_ID_INTEL_82801DB_3;
177
178	/* Determine the address of the SMBus areas */
179	if (force_addr) {
180	i801_smba = force_addr & 0xfff0;
181	} else {
182	pci_read_config_word(I801_dev, SMBBA, &i801_smba);
183	i801_smba &= 0xfff0;
184	if(i801_smba == 0) {
185	dev_err(dev, "SMB base address uninitialized "
186	"- upgrade BIOS or use force_addr=0xaddr\n");
187	return -ENODEV;
188	}
189	}
190
191	if (!request_region(i801_smba, (isich4 ? 16 : 8), i801_driver.name)) {
192	dev_err(dev, "I801_smb region 0x%x already in use!\n",
193	i801_smba);
194	error_return = -EBUSY;
195	goto END;
196	}
197
198	pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
199	temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
200	pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
201
202	/* If force_addr is set, we program the new address here. Just to make
203	sure, we disable the device first. */
204	if (force_addr) {
205	pci_write_config_byte(I801_dev, SMBHSTCFG, temp & 0xfe);
206	pci_write_config_word(I801_dev, SMBBA, i801_smba);
207	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 0x01);
208	dev_warn(dev, "WARNING: I801 SMBus interface set to "
209	"new address %04x!\n", i801_smba);
210	} else if ((temp & 1) == 0) {
211	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 1);
212	dev_warn(dev, "enabling SMBus device\n");
213	}
214
215	if (temp & 0x02)
216	dev_dbg(dev, "I801 using Interrupt SMI# for SMBus.\n");
217	else
218	dev_dbg(dev, "I801 using PCI Interrupt for SMBus.\n");
219
220	pci_read_config_byte(I801_dev, SMBREV, &temp);
221	dev_dbg(dev, "SMBREV = 0x%X\n", temp);
222	dev_dbg(dev, "I801_smba = 0x%X\n", i801_smba);
223
224	END:
225	return error_return;
226	}
227
228
229	static int i801_transaction(void)
230	{
231	int temp;
232	int result = 0;
233	int timeout = 0;
234
235	dev_dbg(I801_dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
236	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
237	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
238	inb_p(SMBHSTDAT1));
239
240	/* Make sure the SMBus host is ready to start transmitting */
241	/* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
242	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
243	dev_dbg(I801_dev, "SMBus busy (%02x). Resetting...\n",
244	temp);
245	outb_p(temp, SMBHSTSTS);
246	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
247	dev_dbg(I801_dev, "Failed! (%02x)\n", temp);
248	return -1;
249	} else {
250	dev_dbg(I801_dev, "Successfull!\n");
251	}
252	}
253
254	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
255
256	/* We will always wait for a fraction of a second! */
257	do {
258	i2c_delay(1);
259	temp = inb_p(SMBHSTSTS);
260	} while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
261
262	/* If the SMBus is still busy, we give up */
263	if (timeout >= MAX_TIMEOUT) {
264	dev_dbg(I801_dev, "SMBus Timeout!\n");
265	result = -1;
266	}
267
268	if (temp & 0x10) {
269	result = -1;
270	dev_dbg(I801_dev, "Error: Failed bus transaction\n");
271	}
272
273	if (temp & 0x08) {
274	result = -1;
275	dev_err(I801_dev, "Bus collision! SMBus may be locked "
276	"until next hard reset. (sorry!)\n");
277	/* Clock stops and slave is stuck in mid-transmission */
278	}
279
280	if (temp & 0x04) {
281	result = -1;
282	dev_dbg(I801_dev, "Error: no response!\n");
283	}
284
285	if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
286	outb_p(inb(SMBHSTSTS), SMBHSTSTS);
287
288	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
289	dev_dbg(I801_dev, "Failed reset at end of transaction "
290	"(%02x)\n", temp);
291	}
292	dev_dbg(I801_dev, "Transaction (post): CNT=%02x, CMD=%02x, "
293	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
294	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
295	inb_p(SMBHSTDAT1));
296	return result;
297	}
298
299	/* All-inclusive block transaction function */
300	static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
301	int command)
302	{
303	int i, len;
304	int smbcmd;
305	int temp;
306	int result = 0;
307	int timeout;
308	unsigned char hostc, errmask;
309
310	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
311	if (read_write == I2C_SMBUS_WRITE) {
312	/* set I2C_EN bit in configuration register */
313	pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
314	pci_write_config_byte(I801_dev, SMBHSTCFG,
315	hostc \| SMBHSTCFG_I2C_EN);
316	} else if (!isich5) {
317	dev_err(I801_dev,
318	"I2C_SMBUS_I2C_BLOCK_READ unsupported!\n");
319	return -1;
320	}
321	}
322
323	if (read_write == I2C_SMBUS_WRITE) {
324	len = data->block[0];
325	if (len < 1)
326	len = 1;
327	if (len > 32)
328	len = 32;
329	outb_p(len, SMBHSTDAT0);
330	outb_p(data->block[1], SMBBLKDAT);
331	} else {
332	len = 32; /* max for reads */
333	}
334
335	if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
336	/* set 32 byte buffer */
337	}
338
339	for (i = 1; i <= len; i++) {
340	if (i == len && read_write == I2C_SMBUS_READ)
341	smbcmd = I801_BLOCK_LAST;
342	else if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
343	read_write == I2C_SMBUS_READ)
344	smbcmd = I801_I2C_BLOCK_DATA;
345	else
346	smbcmd = I801_BLOCK_DATA;
347	outb_p(smbcmd \| ENABLE_INT9, SMBHSTCNT);
348
349	dev_dbg(I801_dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
350	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
351	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
352	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
353
354	/* Make sure the SMBus host is ready to start transmitting */
355	temp = inb_p(SMBHSTSTS);
356	if (i == 1) {
357	/* Erronenous conditions before transaction:
358	* Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
359	errmask=0x9f;
360	} else {
361	/* Erronenous conditions during transaction:
362	* Failed, Bus_Err, Dev_Err, Intr */
363	errmask=0x1e;
364	}
365	if (temp & errmask) {
366	dev_dbg(I801_dev, "SMBus busy (%02x). "
367	"Resetting...\n", temp);
368	outb_p(temp, SMBHSTSTS);
369	if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
370	dev_err(I801_dev,
371	"Reset failed! (%02x)\n", temp);
372	result = -1;
373	goto END;
374	}
375	if (i != 1) {
376	/* if die in middle of block transaction, fail */
377	result = -1;
378	goto END;
379	}
380	}
381
382	if (i == 1)
383	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
384
385	/* We will always wait for a fraction of a second! */
386	timeout = 0;
387	do {
388	temp = inb_p(SMBHSTSTS);
389	i2c_delay(1);
390	}
391	while ((!(temp & 0x80))
392	&& (timeout++ < MAX_TIMEOUT));
393
394	/* If the SMBus is still busy, we give up */
395	if (timeout >= MAX_TIMEOUT) {
396	result = -1;
397	dev_dbg(I801_dev, "SMBus Timeout!\n");
398	}
399
400	if (temp & 0x10) {
401	result = -1;
402	dev_dbg(I801_dev,
403	"Error: Failed bus transaction\n");
404	} else if (temp & 0x08) {
405	result = -1;
406	dev_err(I801_dev, "Bus collision!\n");
407	} else if (temp & 0x04) {
408	result = -1;
409	dev_dbg(I801_dev, "Error: no response!\n");
410	}
411
412	if (i == 1 && read_write == I2C_SMBUS_READ) {
413	if (command != I2C_SMBUS_I2C_BLOCK_DATA) {
414	len = inb_p(SMBHSTDAT0);
415	if (len < 1)
416	len = 1;
417	if (len > 32)
418	len = 32;
419	data->block[0] = len;
420	} else {
421	/* if slave returns < 32 bytes transaction will fail */
422	data->block[0] = 32;
423	}
424	}
425
426	/* Retrieve/store value in SMBBLKDAT */
427	if (read_write == I2C_SMBUS_READ)
428	data->block[i] = inb_p(SMBBLKDAT);
429	if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
430	outb_p(data->block[i+1], SMBBLKDAT);
431	if ((temp & 0x9e) != 0x00)
432	outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
433
434	if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
435	dev_dbg(I801_dev,
436	"Bad status (%02x) at end of transaction\n",
437	temp);
438	}
439	dev_dbg(I801_dev, "Block (post %d): CNT=%02x, CMD=%02x, "
440	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
441	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
442	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
443
444	if (result < 0)
445	goto END;
446	}
447
448	#ifdef HAVE_PEC
449	if(isich4 && command == I2C_SMBUS_BLOCK_DATA_PEC) {
450	/* wait for INTR bit as advised by Intel */
451	timeout = 0;
452	do {
453	temp = inb_p(SMBHSTSTS);
454	i2c_delay(1);
455	} while ((!(temp & 0x02))
456	&& (timeout++ < MAX_TIMEOUT));
457
458	if (timeout >= MAX_TIMEOUT) {
459	dev_dbg(I801_dev, "PEC Timeout!\n");
460	}
461	outb_p(temp, SMBHSTSTS);
462	}
463	#endif
464	result = 0;
465	END:
466	if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
467	read_write == I2C_SMBUS_WRITE) {
468	/* restore saved configuration register value */
469	pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
470	}
471	return result;
472	}
473
474	/* Return -1 on error. */
475	static s32 i801_access(struct i2c_adapter * adap, u16 addr,
476	unsigned short flags, char read_write, u8 command,
477	int size, union i2c_smbus_data * data)
478	{
479	int hwpec = 0;
480	int block = 0;
481	int ret, xact = 0;
482
483	#ifdef HAVE_PEC
484	if(isich4)
485	hwpec = (flags & I2C_CLIENT_PEC) != 0;
486	#endif
487
488	switch (size) {
489	case I2C_SMBUS_QUICK:
490	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
491	SMBHSTADD);
492	xact = I801_QUICK;
493	break;
494	case I2C_SMBUS_BYTE:
495	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
496	SMBHSTADD);
497	if (read_write == I2C_SMBUS_WRITE)
498	outb_p(command, SMBHSTCMD);
499	xact = I801_BYTE;
500	break;
501	case I2C_SMBUS_BYTE_DATA:
502	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
503	SMBHSTADD);
504	outb_p(command, SMBHSTCMD);
505	if (read_write == I2C_SMBUS_WRITE)
506	outb_p(data->byte, SMBHSTDAT0);
507	xact = I801_BYTE_DATA;
508	break;
509	case I2C_SMBUS_WORD_DATA:
510	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
511	SMBHSTADD);
512	outb_p(command, SMBHSTCMD);
513	if (read_write == I2C_SMBUS_WRITE) {
514	outb_p(data->word & 0xff, SMBHSTDAT0);
515	outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
516	}
517	xact = I801_WORD_DATA;
518	break;
519	case I2C_SMBUS_BLOCK_DATA:
520	case I2C_SMBUS_I2C_BLOCK_DATA:
521	#ifdef HAVE_PEC
522	case I2C_SMBUS_BLOCK_DATA_PEC:
523	if(hwpec && size == I2C_SMBUS_BLOCK_DATA)
524	size = I2C_SMBUS_BLOCK_DATA_PEC;
525	#endif
526	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
527	SMBHSTADD);
528	outb_p(command, SMBHSTCMD);
529	block = 1;
530	break;
531	case I2C_SMBUS_PROC_CALL:
532	default:
533	dev_err(I801_dev, "Unsupported transaction %d\n", size);
534	return -1;
535	}
536
537	#ifdef HAVE_PEC
538	if(isich4 && hwpec) {
539	if(size != I2C_SMBUS_QUICK &&
540	size != I2C_SMBUS_I2C_BLOCK_DATA)
541	outb_p(1, SMBAUXCTL); /* enable HW PEC */
542	}
543	#endif
544	if(block)
545	ret = i801_block_transaction(data, read_write, size);
546	else {
547	outb_p(xact \| ENABLE_INT9, SMBHSTCNT);
548	ret = i801_transaction();
549	}
550
551	#ifdef HAVE_PEC
552	if(isich4 && hwpec) {
553	if(size != I2C_SMBUS_QUICK &&
554	size != I2C_SMBUS_I2C_BLOCK_DATA)
555	outb_p(0, SMBAUXCTL);
556	}
557	#endif
558
559	if(block)
560	return ret;
561	if(ret)
562	return -1;
563	if ((read_write == I2C_SMBUS_WRITE) \|\| (xact == I801_QUICK))
564	return 0;
565
566	switch (xact & 0x7f) {
567	case I801_BYTE: /* Result put in SMBHSTDAT0 */
568	case I801_BYTE_DATA:
569	data->byte = inb_p(SMBHSTDAT0);
570	break;
571	case I801_WORD_DATA:
572	data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
573	break;
574	}
575	return 0;
576	}
577
578	static void i801_inc(struct i2c_adapter *adapter)
579	{
580	#ifdef MODULE
581	MOD_INC_USE_COUNT;
582	#endif
583	}
584
585	static void i801_dec(struct i2c_adapter *adapter)
586	{
587	#ifdef MODULE
588	MOD_DEC_USE_COUNT;
589	#endif
590	}
591
592	static u32 i801_func(struct i2c_adapter *adapter)
593	{
594	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
595	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
596	I2C_FUNC_SMBUS_BLOCK_DATA \| I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
597	#ifdef HAVE_PEC
598	\| (isich4 ? I2C_FUNC_SMBUS_HWPEC_CALC : 0)
599	#endif
600	#if 0
601	\| (isich5 ? I2C_FUNC_SMBUS_READ_I2C_BLOCK
602	: 0)
603	#endif
604	;
605	}
606
607	static struct i2c_algorithm smbus_algorithm = {
608	.name = "Non-I2C SMBus adapter",
609	.id = I2C_ALGO_SMBUS,
610	.smbus_xfer = i801_access,
611	.functionality = i801_func,
612	};
613
614	static struct i2c_adapter i801_adapter = {
615	.id = I2C_ALGO_SMBUS \| I2C_HW_SMBUS_I801,
616	.algo = &smbus_algorithm,
617	.inc_use = i801_inc,
618	.dec_use = i801_dec,
619	};
620
621	static struct pci_device_id i801_ids[] __devinitdata = {
622	{
623	.vendor = PCI_VENDOR_ID_INTEL,
624	.device = PCI_DEVICE_ID_INTEL_82801AA_3,
625	.subvendor = PCI_ANY_ID,
626	.subdevice = PCI_ANY_ID,
627	},
628	{
629	.vendor = PCI_VENDOR_ID_INTEL,
630	.device = PCI_DEVICE_ID_INTEL_82801AB_3,
631	.subvendor = PCI_ANY_ID,
632	.subdevice = PCI_ANY_ID,
633	},
634	{
635	.vendor = PCI_VENDOR_ID_INTEL,
636	.device = PCI_DEVICE_ID_INTEL_82801BA_2,
637	.subvendor = PCI_ANY_ID,
638	.subdevice = PCI_ANY_ID,
639	},
640	{
641	.vendor = PCI_VENDOR_ID_INTEL,
642	.device = PCI_DEVICE_ID_INTEL_82801CA_3,
643	.subvendor = PCI_ANY_ID,
644	.subdevice = PCI_ANY_ID,
645	},
646	{
647	.vendor = PCI_VENDOR_ID_INTEL,
648	.device = PCI_DEVICE_ID_INTEL_82801DB_3,
649	.subvendor = PCI_ANY_ID,
650	.subdevice = PCI_ANY_ID,
651	},
652	{
653	.vendor = PCI_VENDOR_ID_INTEL,
654	.device = PCI_DEVICE_ID_INTEL_82801EB_3,
655	.subvendor = PCI_ANY_ID,
656	.subdevice = PCI_ANY_ID,
657	},
658	{
659	.vendor = PCI_VENDOR_ID_INTEL,
660	.device = PCI_DEVICE_ID_INTEL_ESB_4,
661	.subvendor = PCI_ANY_ID,
662	.subdevice = PCI_ANY_ID,
663	},
664	{
665	.vendor = PCI_VENDOR_ID_INTEL,
666	.device = PCI_DEVICE_ID_INTEL_ESB2_17,
667	.subvendor = PCI_ANY_ID,
668	.subdevice = PCI_ANY_ID,
669	},
670	{
671	.vendor = PCI_VENDOR_ID_INTEL,
672	.device = PCI_DEVICE_ID_INTEL_ICH6_16,
673	.subvendor = PCI_ANY_ID,
674	.subdevice = PCI_ANY_ID,
675	},
676	{
677	.vendor = PCI_VENDOR_ID_INTEL,
678	.device = PCI_DEVICE_ID_INTEL_ICH7_17,
679	.subvendor = PCI_ANY_ID,
680	.subdevice = PCI_ANY_ID,
681	},
682	{ 0, }
683	};
684
685	static int __devinit i801_probe(struct pci_dev dev, const struct pci_device_id id)
686	{
687
688	if (i801_setup(dev)) {
689	dev_warn(dev,
690	"I801 not detected, module not inserted.\n");
691	return -ENODEV;
692	}
693
694	snprintf(i801_adapter.name, 32,
695	"SMBus I801 adapter at %04x", i801_smba);
696	return i2c_add_adapter(&i801_adapter);
697	}
698
699	static void __devexit i801_remove(struct pci_dev *dev)
700	{
701	i2c_del_adapter(&i801_adapter);
702	release_region(i801_smba, (isich4 ? 16 : 8));
703	}
704
705	static struct pci_driver i801_driver = {
706	.name = "i801 smbus",
707	.id_table = i801_ids,
708	.probe = i801_probe,
709	.remove = __devexit_p(i801_remove),
710	};
711
712	static int __init i2c_i801_init(void)
713	{
714	printk(KERN_INFO "i2c-i801 version %s (%s)\n", LM_VERSION, LM_DATE);
715	return pci_module_init(&i801_driver);
716	}
717
718	static void __exit i2c_i801_exit(void)
719	{
720	pci_unregister_driver(&i801_driver);
721	}
722
723	MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
724	"Philip Edelbrock <phil@netroedge.com>, "
725	"and Mark D. Studebaker <mdsxyz123@yahoo.com>");
726	MODULE_DESCRIPTION("I801 SMBus driver");
727	MODULE_LICENSE("GPL");
728
729	module_init(i2c_i801_init);
730	module_exit(i2c_i801_exit);

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