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i2c-i801.c @ 2992

Revision 2992, 18.9 KB (checked in by ruik, 8 years ago)
Added new Intel southbridge known as ESB2
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`

Line
1	/*
2	i801.c - Part of lm_sensors, Linux kernel modules for hardware
3	monitoring
4	Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5	Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
6	<mdsxyz123@yahoo.com>
7
8	This program is free software; you can redistribute it and/or modify
9	it under the terms of the GNU General Public License as published by
10	the Free Software Foundation; either version 2 of the License, or
11	(at your option) any later version.
12
13	This program is distributed in the hope that it will be useful,
14	but WITHOUT ANY WARRANTY; without even the implied warranty of
15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	GNU General Public License for more details.
17
18	You should have received a copy of the GNU General Public License
19	along with this program; if not, write to the Free Software
20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21	*/
22
23	/*
24	SUPPORTED DEVICES PCI ID
25	82801AA 2413
26	82801AB 2423
27	82801BA 2443
28	82801CA/CAM 2483
29	82801DB 24C3 (HW PEC supported, 32 byte buffer not supported)
30	82801EB 24D3 (HW PEC supported, 32 byte buffer not supported)
31	6300ESB 25A4 ("")
32	ICH6 266A ("")
33	ICH7 27DA ("")
34	ESB2 269B ("")
35	This driver supports several versions of Intel's I/O Controller Hubs (ICH).
36	For SMBus support, they are similar to the PIIX4 and are part
37	of Intel's '810' and other chipsets.
38	See the doc/busses/i2c-i801 file for details.
39	I2C Block Read supported for ICH5 and higher.
40	Block Process Call are not supported.
41	*/
42
43	/* Note: we assume there can only be one I801, with one SMBus interface */
44
45	/* #define DEBUG 1 */
46
47	#include <linux/module.h>
48	#include <linux/pci.h>
49	#include <linux/kernel.h>
50	#include <linux/stddef.h>
51	#include <linux/sched.h>
52	#include <linux/ioport.h>
53	#include <linux/init.h>
54	#include <linux/i2c.h>
55	#include <asm/io.h>
56	#include "version.h"
57	#include "sensors_compat.h"
58
59	/* 82801CA is undefined before kernel 2.4.13 */
60	#ifndef PCI_DEVICE_ID_INTEL_82801CA_3
61	#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483
62	#endif
63
64	/* 82801DB is undefined before kernel 2.4.19 */
65	#ifndef PCI_DEVICE_ID_INTEL_82801DB_3
66	#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3
67	#endif
68
69	/* 82801EB is undefined before kernel 2.4.21 */
70	#ifndef PCI_DEVICE_ID_INTEL_82801EB_3
71	#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3
72	#endif
73
74	/* ESB is undefined before kernel 2.4.22 */
75	#ifndef PCI_DEVICE_ID_INTEL_ESB_4
76	#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4
77	#endif
78
79	/* ESB2 - Enterprise Southbridge is undefined */
80	#ifndef PCI_DEVICE_ID_INTEL_ESB2_17
81	#define PCI_DEVICE_ID_INTEL_ESB2_17 0x269b
82	#endif
83
84	/* ICH6 is undefined */
85	#ifndef PCI_DEVICE_ID_INTEL_ICH6_16
86	#define PCI_DEVICE_ID_INTEL_ICH6_16 0x266a
87	#endif
88
89	/* ICH7 is undefined */
90	#ifndef PCI_DEVICE_ID_INTEL_ICH7_17
91	#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da
92	#endif
93
94	#ifdef I2C_FUNC_SMBUS_BLOCK_DATA_PEC
95	#define HAVE_PEC
96	#endif
97
98	/* I801 SMBus address offsets */
99	#define SMBHSTSTS (0 + i801_smba)
100	#define SMBHSTCNT (2 + i801_smba)
101	#define SMBHSTCMD (3 + i801_smba)
102	#define SMBHSTADD (4 + i801_smba)
103	#define SMBHSTDAT0 (5 + i801_smba)
104	#define SMBHSTDAT1 (6 + i801_smba)
105	#define SMBBLKDAT (7 + i801_smba)
106	#define SMBPEC (8 + i801_smba) /* ICH4 only */
107	#define SMBAUXSTS (12 + i801_smba) /* ICH4 only */
108	#define SMBAUXCTL (13 + i801_smba) /* ICH4 only */
109
110	/* PCI Address Constants */
111	#define SMBBA 0x020
112	#define SMBHSTCFG 0x040
113	#define SMBREV 0x008
114
115	/* Host configuration bits for SMBHSTCFG */
116	#define SMBHSTCFG_HST_EN 1
117	#define SMBHSTCFG_SMB_SMI_EN 2
118	#define SMBHSTCFG_I2C_EN 4
119
120	/* Other settings */
121	#define MAX_TIMEOUT 100
122	#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
123
124	/* I801 command constants */
125	#define I801_QUICK 0x00
126	#define I801_BYTE 0x04
127	#define I801_BYTE_DATA 0x08
128	#define I801_WORD_DATA 0x0C
129	#define I801_PROC_CALL 0x10 /* later chips only, unimplemented */
130	#define I801_BLOCK_DATA 0x14
131	#define I801_I2C_BLOCK_DATA 0x18 /* ich4 and later */
132	#define I801_BLOCK_LAST 0x34
133	#define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */
134	#define I801_START 0x40
135	#define I801_PEC_EN 0x80 /* ich4 and later */
136
137	/* insmod parameters */
138
139	/* If force_addr is set to anything different from 0, we forcibly enable
140	the I801 at the given address. VERY DANGEROUS! */
141	static int force_addr = 0;
142	MODULE_PARM(force_addr, "i");
143	MODULE_PARM_DESC(force_addr,
144	"Forcibly enable the I801 at the given address. "
145	"EXTREMELY DANGEROUS!");
146
147	static int i801_transaction(void);
148	static int i801_block_transaction(union i2c_smbus_data *data,
149	char read_write, int command);
150
151	static unsigned short i801_smba;
152	static struct pci_dev *I801_dev;
153	static int isich4; /* is PEC supported? */
154	static int isich5; /* is i2c block read supported? */
155
156	static int i801_setup(struct pci_dev *dev)
157	{
158	int error_return = 0;
159	unsigned char temp;
160
161	/* Note: we keep on searching until we have found 'function 3' */
162	if(PCI_FUNC(dev->devfn) != 3)
163	return -ENODEV;
164
165	I801_dev = dev;
166	if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_3 \|\|
167	dev->device == PCI_DEVICE_ID_INTEL_82801EB_3 \|\|
168	dev->device == PCI_DEVICE_ID_INTEL_ESB_4 \|\|
169	dev->device == PCI_DEVICE_ID_INTEL_ESB2_17 \|\|
170	dev->device == PCI_DEVICE_ID_INTEL_ICH6_16 \|\|
171	dev->device == PCI_DEVICE_ID_INTEL_ICH7_17)
172	isich4 = 1;
173	else
174	isich4 = 0;
175	isich5 = isich4 && dev->device != PCI_DEVICE_ID_INTEL_82801DB_3;
176
177	/* Determine the address of the SMBus areas */
178	if (force_addr) {
179	i801_smba = force_addr & 0xfff0;
180	} else {
181	pci_read_config_word(I801_dev, SMBBA, &i801_smba);
182	i801_smba &= 0xfff0;
183	if(i801_smba == 0) {
184	dev_err(dev, "SMB base address uninitialized"
185	"- upgrade BIOS or use force_addr=0xaddr\n");
186	return -ENODEV;
187	}
188	}
189
190	if (!request_region(i801_smba, (isich4 ? 16 : 8), "i801-smbus")) {
191	dev_err(dev, "I801_smb region 0x%x already in use!\n",
192	i801_smba);
193	error_return = -EBUSY;
194	goto END;
195	}
196
197	pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
198	temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
199	pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
200
201	/* If force_addr is set, we program the new address here. Just to make
202	sure, we disable the device first. */
203	if (force_addr) {
204	pci_write_config_byte(I801_dev, SMBHSTCFG, temp & 0xfe);
205	pci_write_config_word(I801_dev, SMBBA, i801_smba);
206	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 0x01);
207	dev_warn(dev, "WARNING: I801 SMBus interface set to "
208	"new address %04x!\n", i801_smba);
209	} else if ((temp & 1) == 0) {
210	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 1);
211	dev_warn(dev, "enabling SMBus device\n");
212	}
213
214	if (temp & 0x02)
215	dev_dbg(dev, "I801 using Interrupt SMI# for SMBus.\n");
216	else
217	dev_dbg(dev, "I801 using PCI Interrupt for SMBus.\n");
218
219	pci_read_config_byte(I801_dev, SMBREV, &temp);
220	dev_dbg(dev, "SMBREV = 0x%X\n", temp);
221	dev_dbg(dev, "I801_smba = 0x%X\n", i801_smba);
222
223	END:
224	return error_return;
225	}
226
227
228	static int i801_transaction(void)
229	{
230	int temp;
231	int result = 0;
232	int timeout = 0;
233
234	dev_dbg(I801_dev, "Transaction (pre): CNT=%02x, CMD=%02x,"
235	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
236	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
237	inb_p(SMBHSTDAT1));
238
239	/* Make sure the SMBus host is ready to start transmitting */
240	/* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
241	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
242	dev_dbg(I801_dev, "SMBus busy (%02x). Resetting... \n",
243	temp);
244	outb_p(temp, SMBHSTSTS);
245	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
246	dev_dbg(I801_dev, "Failed! (%02x)\n", temp);
247	return -1;
248	} else {
249	dev_dbg(I801_dev, "Successfull!\n");
250	}
251	}
252
253	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
254
255	/* We will always wait for a fraction of a second! */
256	do {
257	i2c_delay(1);
258	temp = inb_p(SMBHSTSTS);
259	} while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
260
261	/* If the SMBus is still busy, we give up */
262	if (timeout >= MAX_TIMEOUT) {
263	dev_dbg(I801_dev, "SMBus Timeout!\n");
264	result = -1;
265	}
266
267	if (temp & 0x10) {
268	result = -1;
269	dev_dbg(I801_dev, "Error: Failed bus transaction\n");
270	}
271
272	if (temp & 0x08) {
273	result = -1;
274	dev_err(I801_dev, "Bus collision! SMBus may be locked "
275	"until next hard reset. (sorry!)\n");
276	/* Clock stops and slave is stuck in mid-transmission */
277	}
278
279	if (temp & 0x04) {
280	result = -1;
281	dev_dbg(I801_dev, "Error: no response!\n");
282	}
283
284	if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
285	outb_p(inb(SMBHSTSTS), SMBHSTSTS);
286
287	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
288	dev_dbg(I801_dev, "Failed reset at end of transaction"
289	"(%02x)\n", temp);
290	}
291	dev_dbg(I801_dev, "Transaction (post): CNT=%02x, CMD=%02x, "
292	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
293	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
294	inb_p(SMBHSTDAT1));
295	return result;
296	}
297
298	/* All-inclusive block transaction function */
299	static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
300	int command)
301	{
302	int i, len;
303	int smbcmd;
304	int temp;
305	int result = 0;
306	int timeout;
307	unsigned char hostc, errmask;
308
309	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
310	if (read_write == I2C_SMBUS_WRITE) {
311	/* set I2C_EN bit in configuration register */
312	pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
313	pci_write_config_byte(I801_dev, SMBHSTCFG,
314	hostc \| SMBHSTCFG_I2C_EN);
315	} else if (!isich5) {
316	dev_err(I801_dev,
317	"I2C_SMBUS_I2C_BLOCK_READ unsupported!\n");
318	return -1;
319	}
320	}
321
322	if (read_write == I2C_SMBUS_WRITE) {
323	len = data->block[0];
324	if (len < 1)
325	len = 1;
326	if (len > 32)
327	len = 32;
328	outb_p(len, SMBHSTDAT0);
329	outb_p(data->block[1], SMBBLKDAT);
330	} else {
331	len = 32; /* max for reads */
332	}
333
334	if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
335	/* set 32 byte buffer */
336	}
337
338	for (i = 1; i <= len; i++) {
339	if (i == len && read_write == I2C_SMBUS_READ)
340	smbcmd = I801_BLOCK_LAST;
341	else if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
342	read_write == I2C_SMBUS_READ)
343	smbcmd = I801_I2C_BLOCK_DATA;
344	else
345	smbcmd = I801_BLOCK_DATA;
346	outb_p(smbcmd \| ENABLE_INT9, SMBHSTCNT);
347
348	dev_dbg(I801_dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
349	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
350	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
351	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
352
353	/* Make sure the SMBus host is ready to start transmitting */
354	temp = inb_p(SMBHSTSTS);
355	if (i == 1) {
356	/* Erronenous conditions before transaction:
357	* Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
358	errmask=0x9f;
359	} else {
360	/* Erronenous conditions during transaction:
361	* Failed, Bus_Err, Dev_Err, Intr */
362	errmask=0x1e;
363	}
364	if (temp & errmask) {
365	dev_dbg(I801_dev, "SMBus busy (%02x). "
366	"Resetting... \n", temp);
367	outb_p(temp, SMBHSTSTS);
368	if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
369	dev_err(I801_dev,
370	"Reset failed! (%02x)\n", temp);
371	result = -1;
372	goto END;
373	}
374	if (i != 1) {
375	/* if die in middle of block transaction, fail */
376	result = -1;
377	goto END;
378	}
379	}
380
381	if (i == 1)
382	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
383
384	/* We will always wait for a fraction of a second! */
385	timeout = 0;
386	do {
387	temp = inb_p(SMBHSTSTS);
388	i2c_delay(1);
389	}
390	while ((!(temp & 0x80))
391	&& (timeout++ < MAX_TIMEOUT));
392
393	/* If the SMBus is still busy, we give up */
394	if (timeout >= MAX_TIMEOUT) {
395	result = -1;
396	dev_dbg(I801_dev, "SMBus Timeout!\n");
397	}
398
399	if (temp & 0x10) {
400	result = -1;
401	dev_dbg(I801_dev,
402	"Error: Failed bus transaction\n");
403	} else if (temp & 0x08) {
404	result = -1;
405	dev_err(I801_dev, "Bus collision!\n");
406	} else if (temp & 0x04) {
407	result = -1;
408	dev_dbg(I801_dev, "Error: no response!\n");
409	}
410
411	if (i == 1 && read_write == I2C_SMBUS_READ) {
412	if (command != I2C_SMBUS_I2C_BLOCK_DATA) {
413	len = inb_p(SMBHSTDAT0);
414	if (len < 1)
415	len = 1;
416	if (len > 32)
417	len = 32;
418	data->block[0] = len;
419	} else {
420	/* if slave returns < 32 bytes transaction will fail */
421	data->block[0] = 32;
422	}
423	}
424
425	/* Retrieve/store value in SMBBLKDAT */
426	if (read_write == I2C_SMBUS_READ)
427	data->block[i] = inb_p(SMBBLKDAT);
428	if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
429	outb_p(data->block[i+1], SMBBLKDAT);
430	if ((temp & 0x9e) != 0x00)
431	outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
432
433	if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
434	dev_dbg(I801_dev,
435	"Bad status (%02x) at end of transaction\n",
436	temp);
437	}
438	dev_dbg(I801_dev, "Block (post %d): CNT=%02x, CMD=%02x, "
439	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
440	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
441	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
442
443	if (result < 0)
444	goto END;
445	}
446
447	#ifdef HAVE_PEC
448	if(isich4 && command == I2C_SMBUS_BLOCK_DATA_PEC) {
449	/* wait for INTR bit as advised by Intel */
450	timeout = 0;
451	do {
452	temp = inb_p(SMBHSTSTS);
453	i2c_delay(1);
454	} while ((!(temp & 0x02))
455	&& (timeout++ < MAX_TIMEOUT));
456
457	if (timeout >= MAX_TIMEOUT) {
458	dev_dbg(I801_dev, "PEC Timeout!\n");
459	}
460	outb_p(temp, SMBHSTSTS);
461	}
462	#endif
463	result = 0;
464	END:
465	if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
466	read_write == I2C_SMBUS_WRITE) {
467	/* restore saved configuration register value */
468	pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
469	}
470	return result;
471	}
472
473	/* Return -1 on error. */
474	static s32 i801_access(struct i2c_adapter * adap, u16 addr,
475	unsigned short flags, char read_write, u8 command,
476	int size, union i2c_smbus_data * data)
477	{
478	int hwpec = 0;
479	int block = 0;
480	int ret, xact = 0;
481
482	#ifdef HAVE_PEC
483	if(isich4)
484	hwpec = (flags & I2C_CLIENT_PEC) != 0;
485	#endif
486
487	switch (size) {
488	case I2C_SMBUS_QUICK:
489	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
490	SMBHSTADD);
491	xact = I801_QUICK;
492	break;
493	case I2C_SMBUS_BYTE:
494	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
495	SMBHSTADD);
496	if (read_write == I2C_SMBUS_WRITE)
497	outb_p(command, SMBHSTCMD);
498	xact = I801_BYTE;
499	break;
500	case I2C_SMBUS_BYTE_DATA:
501	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
502	SMBHSTADD);
503	outb_p(command, SMBHSTCMD);
504	if (read_write == I2C_SMBUS_WRITE)
505	outb_p(data->byte, SMBHSTDAT0);
506	xact = I801_BYTE_DATA;
507	break;
508	case I2C_SMBUS_WORD_DATA:
509	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
510	SMBHSTADD);
511	outb_p(command, SMBHSTCMD);
512	if (read_write == I2C_SMBUS_WRITE) {
513	outb_p(data->word & 0xff, SMBHSTDAT0);
514	outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
515	}
516	xact = I801_WORD_DATA;
517	break;
518	case I2C_SMBUS_BLOCK_DATA:
519	case I2C_SMBUS_I2C_BLOCK_DATA:
520	#ifdef HAVE_PEC
521	case I2C_SMBUS_BLOCK_DATA_PEC:
522	if(hwpec && size == I2C_SMBUS_BLOCK_DATA)
523	size = I2C_SMBUS_BLOCK_DATA_PEC;
524	#endif
525	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
526	SMBHSTADD);
527	outb_p(command, SMBHSTCMD);
528	block = 1;
529	break;
530	case I2C_SMBUS_PROC_CALL:
531	default:
532	dev_err(I801_dev, "Unsupported transaction %d\n", size);
533	return -1;
534	}
535
536	#ifdef HAVE_PEC
537	if(isich4 && hwpec) {
538	if(size != I2C_SMBUS_QUICK &&
539	size != I2C_SMBUS_I2C_BLOCK_DATA)
540	outb_p(1, SMBAUXCTL); /* enable HW PEC */
541	}
542	#endif
543	if(block)
544	ret = i801_block_transaction(data, read_write, size);
545	else {
546	outb_p(xact \| ENABLE_INT9, SMBHSTCNT);
547	ret = i801_transaction();
548	}
549
550	#ifdef HAVE_PEC
551	if(isich4 && hwpec) {
552	if(size != I2C_SMBUS_QUICK &&
553	size != I2C_SMBUS_I2C_BLOCK_DATA)
554	outb_p(0, SMBAUXCTL);
555	}
556	#endif
557
558	if(block)
559	return ret;
560	if(ret)
561	return -1;
562	if ((read_write == I2C_SMBUS_WRITE) \|\| (xact == I801_QUICK))
563	return 0;
564
565	switch (xact & 0x7f) {
566	case I801_BYTE: /* Result put in SMBHSTDAT0 */
567	case I801_BYTE_DATA:
568	data->byte = inb_p(SMBHSTDAT0);
569	break;
570	case I801_WORD_DATA:
571	data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
572	break;
573	}
574	return 0;
575	}
576
577	static void i801_inc(struct i2c_adapter *adapter)
578	{
579	#ifdef MODULE
580	MOD_INC_USE_COUNT;
581	#endif
582	}
583
584	static void i801_dec(struct i2c_adapter *adapter)
585	{
586	#ifdef MODULE
587	MOD_DEC_USE_COUNT;
588	#endif
589	}
590
591	static u32 i801_func(struct i2c_adapter *adapter)
592	{
593	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
594	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
595	I2C_FUNC_SMBUS_BLOCK_DATA \| I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
596	#ifdef HAVE_PEC
597	\| (isich4 ? I2C_FUNC_SMBUS_BLOCK_DATA_PEC \|
598	I2C_FUNC_SMBUS_HWPEC_CALC
599	: 0)
600	#endif
601	#if 0
602	\| (isich5 ? I2C_FUNC_SMBUS_READ_I2C_BLOCK
603	: 0)
604	#endif
605	;
606	}
607
608	static struct i2c_algorithm smbus_algorithm = {
609	.name = "Non-I2C SMBus adapter",
610	.id = I2C_ALGO_SMBUS,
611	.smbus_xfer = i801_access,
612	.functionality = i801_func,
613	};
614
615	static struct i2c_adapter i801_adapter = {
616	.id = I2C_ALGO_SMBUS \| I2C_HW_SMBUS_I801,
617	.algo = &smbus_algorithm,
618	.name = "unset",
619	.inc_use = i801_inc,
620	.dec_use = i801_dec,
621	};
622
623	static struct pci_device_id i801_ids[] __devinitdata = {
624	{
625	.vendor = PCI_VENDOR_ID_INTEL,
626	.device = PCI_DEVICE_ID_INTEL_82801AA_3,
627	.subvendor = PCI_ANY_ID,
628	.subdevice = PCI_ANY_ID,
629	},
630	{
631	.vendor = PCI_VENDOR_ID_INTEL,
632	.device = PCI_DEVICE_ID_INTEL_82801AB_3,
633	.subvendor = PCI_ANY_ID,
634	.subdevice = PCI_ANY_ID,
635	},
636	{
637	.vendor = PCI_VENDOR_ID_INTEL,
638	.device = PCI_DEVICE_ID_INTEL_82801BA_2,
639	.subvendor = PCI_ANY_ID,
640	.subdevice = PCI_ANY_ID,
641	},
642	{
643	.vendor = PCI_VENDOR_ID_INTEL,
644	.device = PCI_DEVICE_ID_INTEL_82801CA_3,
645	.subvendor = PCI_ANY_ID,
646	.subdevice = PCI_ANY_ID,
647	},
648	{
649	.vendor = PCI_VENDOR_ID_INTEL,
650	.device = PCI_DEVICE_ID_INTEL_82801DB_3,
651	.subvendor = PCI_ANY_ID,
652	.subdevice = PCI_ANY_ID,
653	},
654	{
655	.vendor = PCI_VENDOR_ID_INTEL,
656	.device = PCI_DEVICE_ID_INTEL_82801EB_3,
657	.subvendor = PCI_ANY_ID,
658	.subdevice = PCI_ANY_ID,
659	},
660	{
661	.vendor = PCI_VENDOR_ID_INTEL,
662	.device = PCI_DEVICE_ID_INTEL_ESB_4,
663	.subvendor = PCI_ANY_ID,
664	.subdevice = PCI_ANY_ID,
665	},
666	{
667	.vendor = PCI_VENDOR_ID_INTEL,
668	.device = PCI_DEVICE_ID_INTEL_ESB2_17,
669	.subvendor = PCI_ANY_ID,
670	.subdevice = PCI_ANY_ID,
671	},
672	{
673	.vendor = PCI_VENDOR_ID_INTEL,
674	.device = PCI_DEVICE_ID_INTEL_ICH6_16,
675	.subvendor = PCI_ANY_ID,
676	.subdevice = PCI_ANY_ID,
677	},
678	{
679	.vendor = PCI_VENDOR_ID_INTEL,
680	.device = PCI_DEVICE_ID_INTEL_ICH7_17,
681	.subvendor = PCI_ANY_ID,
682	.subdevice = PCI_ANY_ID,
683	},
684	{ 0, }
685	};
686
687	static int __devinit i801_probe(struct pci_dev dev, const struct pci_device_id id)
688	{
689
690	if (i801_setup(dev)) {
691	dev_warn(dev,
692	"I801 not detected, module not inserted.\n");
693	return -ENODEV;
694	}
695
696	snprintf(i801_adapter.name, 32,
697	"SMBus I801 adapter at %04x", i801_smba);
698	return i2c_add_adapter(&i801_adapter);
699	}
700
701	static void __devexit i801_remove(struct pci_dev *dev)
702	{
703	i2c_del_adapter(&i801_adapter);
704	release_region(i801_smba, (isich4 ? 16 : 8));
705	}
706
707	static struct pci_driver i801_driver = {
708	.name = "i801 smbus",
709	.id_table = i801_ids,
710	.probe = i801_probe,
711	.remove = __devexit_p(i801_remove),
712	};
713
714	static int __init i2c_i801_init(void)
715	{
716	printk(KERN_INFO "i2c-i801 version %s (%s)\n", LM_VERSION, LM_DATE);
717	return pci_module_init(&i801_driver);
718	}
719
720	static void __exit i2c_i801_exit(void)
721	{
722	pci_unregister_driver(&i801_driver);
723	}
724
725	MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
726	"Philip Edelbrock <phil@netroedge.com>, "
727	"and Mark D. Studebaker <mdsxyz123@yahoo.com>");
728	MODULE_DESCRIPTION("I801 SMBus driver");
729	MODULE_LICENSE("GPL");
730
731	module_init(i2c_i801_init);
732	module_exit(i2c_i801_exit);

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