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i2c-i801.c @ 2897

Revision 2897, 18.5 KB (checked in by mds, 8 years ago)
disable broken read i2c block functionality
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`

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1	/*
2	i801.c - Part of lm_sensors, Linux kernel modules for hardware
3	monitoring
4	Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5	Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
6	<mdsxyz123@yahoo.com>
7
8	This program is free software; you can redistribute it and/or modify
9	it under the terms of the GNU General Public License as published by
10	the Free Software Foundation; either version 2 of the License, or
11	(at your option) any later version.
12
13	This program is distributed in the hope that it will be useful,
14	but WITHOUT ANY WARRANTY; without even the implied warranty of
15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	GNU General Public License for more details.
17
18	You should have received a copy of the GNU General Public License
19	along with this program; if not, write to the Free Software
20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21	*/
22
23	/*
24	SUPPORTED DEVICES PCI ID
25	82801AA 2413
26	82801AB 2423
27	82801BA 2443
28	82801CA/CAM 2483
29	82801DB 24C3 (HW PEC supported, 32 byte buffer not supported)
30	82801EB 24D3 (HW PEC supported, 32 byte buffer not supported)
31	6300ESB 25A4 ("")
32	ICH6 266A ("")
33	ICH7 27DA ("")
34	This driver supports several versions of Intel's I/O Controller Hubs (ICH).
35	For SMBus support, they are similar to the PIIX4 and are part
36	of Intel's '810' and other chipsets.
37	See the doc/busses/i2c-i801 file for details.
38	I2C Block Read supported for ICH5 and higher.
39	Block Process Call are not supported.
40	*/
41
42	/* Note: we assume there can only be one I801, with one SMBus interface */
43
44	/* #define DEBUG 1 */
45
46	#include <linux/module.h>
47	#include <linux/pci.h>
48	#include <linux/kernel.h>
49	#include <linux/stddef.h>
50	#include <linux/sched.h>
51	#include <linux/ioport.h>
52	#include <linux/init.h>
53	#include <linux/i2c.h>
54	#include <asm/io.h>
55	#include "version.h"
56	#include "sensors_compat.h"
57
58	/* 82801CA is undefined before kernel 2.4.13 */
59	#ifndef PCI_DEVICE_ID_INTEL_82801CA_3
60	#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483
61	#endif
62
63	/* 82801DB is undefined before kernel 2.4.19 */
64	#ifndef PCI_DEVICE_ID_INTEL_82801DB_3
65	#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3
66	#endif
67
68	/* 82801EB is undefined before kernel 2.4.21 */
69	#ifndef PCI_DEVICE_ID_INTEL_82801EB_3
70	#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3
71	#endif
72
73	/* ESB is undefined before kernel 2.4.22 */
74	#ifndef PCI_DEVICE_ID_INTEL_ESB_4
75	#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4
76	#endif
77
78	/* ICH6 is undefined */
79	#ifndef PCI_DEVICE_ID_INTEL_ICH6_16
80	#define PCI_DEVICE_ID_INTEL_ICH6_16 0x266a
81	#endif
82
83	/* ICH7 is undefined */
84	#ifndef PCI_DEVICE_ID_INTEL_ICH7_17
85	#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da
86	#endif
87
88	#ifdef I2C_FUNC_SMBUS_BLOCK_DATA_PEC
89	#define HAVE_PEC
90	#endif
91
92	/* I801 SMBus address offsets */
93	#define SMBHSTSTS (0 + i801_smba)
94	#define SMBHSTCNT (2 + i801_smba)
95	#define SMBHSTCMD (3 + i801_smba)
96	#define SMBHSTADD (4 + i801_smba)
97	#define SMBHSTDAT0 (5 + i801_smba)
98	#define SMBHSTDAT1 (6 + i801_smba)
99	#define SMBBLKDAT (7 + i801_smba)
100	#define SMBPEC (8 + i801_smba) /* ICH4 only */
101	#define SMBAUXSTS (12 + i801_smba) /* ICH4 only */
102	#define SMBAUXCTL (13 + i801_smba) /* ICH4 only */
103
104	/* PCI Address Constants */
105	#define SMBBA 0x020
106	#define SMBHSTCFG 0x040
107	#define SMBREV 0x008
108
109	/* Host configuration bits for SMBHSTCFG */
110	#define SMBHSTCFG_HST_EN 1
111	#define SMBHSTCFG_SMB_SMI_EN 2
112	#define SMBHSTCFG_I2C_EN 4
113
114	/* Other settings */
115	#define MAX_TIMEOUT 100
116	#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
117
118	/* I801 command constants */
119	#define I801_QUICK 0x00
120	#define I801_BYTE 0x04
121	#define I801_BYTE_DATA 0x08
122	#define I801_WORD_DATA 0x0C
123	#define I801_PROC_CALL 0x10 /* later chips only, unimplemented */
124	#define I801_BLOCK_DATA 0x14
125	#define I801_I2C_BLOCK_DATA 0x18 /* ich4 and later */
126	#define I801_BLOCK_LAST 0x34
127	#define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */
128	#define I801_START 0x40
129	#define I801_PEC_EN 0x80 /* ich4 and later */
130
131	/* insmod parameters */
132
133	/* If force_addr is set to anything different from 0, we forcibly enable
134	the I801 at the given address. VERY DANGEROUS! */
135	static int force_addr = 0;
136	MODULE_PARM(force_addr, "i");
137	MODULE_PARM_DESC(force_addr,
138	"Forcibly enable the I801 at the given address. "
139	"EXTREMELY DANGEROUS!");
140
141	static int i801_transaction(void);
142	static int i801_block_transaction(union i2c_smbus_data *data,
143	char read_write, int command);
144
145	static unsigned short i801_smba;
146	static struct pci_dev *I801_dev;
147	static int isich4; /* is PEC supported? */
148	static int isich5; /* is i2c block read supported? */
149
150	static int i801_setup(struct pci_dev *dev)
151	{
152	int error_return = 0;
153	unsigned char temp;
154
155	/* Note: we keep on searching until we have found 'function 3' */
156	if(PCI_FUNC(dev->devfn) != 3)
157	return -ENODEV;
158
159	I801_dev = dev;
160	if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_3 \|\|
161	dev->device == PCI_DEVICE_ID_INTEL_82801EB_3 \|\|
162	dev->device == PCI_DEVICE_ID_INTEL_ESB_4 \|\|
163	dev->device == PCI_DEVICE_ID_INTEL_ICH6_16 \|\|
164	dev->device == PCI_DEVICE_ID_INTEL_ICH7_17)
165	isich4 = 1;
166	else
167	isich4 = 0;
168	isich5 = isich4 && dev->device != PCI_DEVICE_ID_INTEL_82801DB_3;
169
170	/* Determine the address of the SMBus areas */
171	if (force_addr) {
172	i801_smba = force_addr & 0xfff0;
173	} else {
174	pci_read_config_word(I801_dev, SMBBA, &i801_smba);
175	i801_smba &= 0xfff0;
176	if(i801_smba == 0) {
177	dev_err(dev, "SMB base address uninitialized"
178	"- upgrade BIOS or use force_addr=0xaddr\n");
179	return -ENODEV;
180	}
181	}
182
183	if (!request_region(i801_smba, (isich4 ? 16 : 8), "i801-smbus")) {
184	dev_err(dev, "I801_smb region 0x%x already in use!\n",
185	i801_smba);
186	error_return = -EBUSY;
187	goto END;
188	}
189
190	pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
191	temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
192	pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
193
194	/* If force_addr is set, we program the new address here. Just to make
195	sure, we disable the device first. */
196	if (force_addr) {
197	pci_write_config_byte(I801_dev, SMBHSTCFG, temp & 0xfe);
198	pci_write_config_word(I801_dev, SMBBA, i801_smba);
199	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 0x01);
200	dev_warn(dev, "WARNING: I801 SMBus interface set to "
201	"new address %04x!\n", i801_smba);
202	} else if ((temp & 1) == 0) {
203	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 1);
204	dev_warn(dev, "enabling SMBus device\n");
205	}
206
207	if (temp & 0x02)
208	dev_dbg(dev, "I801 using Interrupt SMI# for SMBus.\n");
209	else
210	dev_dbg(dev, "I801 using PCI Interrupt for SMBus.\n");
211
212	pci_read_config_byte(I801_dev, SMBREV, &temp);
213	dev_dbg(dev, "SMBREV = 0x%X\n", temp);
214	dev_dbg(dev, "I801_smba = 0x%X\n", i801_smba);
215
216	END:
217	return error_return;
218	}
219
220
221	static int i801_transaction(void)
222	{
223	int temp;
224	int result = 0;
225	int timeout = 0;
226
227	dev_dbg(I801_dev, "Transaction (pre): CNT=%02x, CMD=%02x,"
228	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
229	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
230	inb_p(SMBHSTDAT1));
231
232	/* Make sure the SMBus host is ready to start transmitting */
233	/* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
234	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
235	dev_dbg(I801_dev, "SMBus busy (%02x). Resetting... \n",
236	temp);
237	outb_p(temp, SMBHSTSTS);
238	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
239	dev_dbg(I801_dev, "Failed! (%02x)\n", temp);
240	return -1;
241	} else {
242	dev_dbg(I801_dev, "Successfull!\n");
243	}
244	}
245
246	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
247
248	/* We will always wait for a fraction of a second! */
249	do {
250	i2c_delay(1);
251	temp = inb_p(SMBHSTSTS);
252	} while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
253
254	/* If the SMBus is still busy, we give up */
255	if (timeout >= MAX_TIMEOUT) {
256	dev_dbg(I801_dev, "SMBus Timeout!\n");
257	result = -1;
258	}
259
260	if (temp & 0x10) {
261	result = -1;
262	dev_dbg(I801_dev, "Error: Failed bus transaction\n");
263	}
264
265	if (temp & 0x08) {
266	result = -1;
267	dev_err(I801_dev, "Bus collision! SMBus may be locked "
268	"until next hard reset. (sorry!)\n");
269	/* Clock stops and slave is stuck in mid-transmission */
270	}
271
272	if (temp & 0x04) {
273	result = -1;
274	dev_dbg(I801_dev, "Error: no response!\n");
275	}
276
277	if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
278	outb_p(inb(SMBHSTSTS), SMBHSTSTS);
279
280	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
281	dev_dbg(I801_dev, "Failed reset at end of transaction"
282	"(%02x)\n", temp);
283	}
284	dev_dbg(I801_dev, "Transaction (post): CNT=%02x, CMD=%02x, "
285	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
286	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
287	inb_p(SMBHSTDAT1));
288	return result;
289	}
290
291	/* All-inclusive block transaction function */
292	static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
293	int command)
294	{
295	int i, len;
296	int smbcmd;
297	int temp;
298	int result = 0;
299	int timeout;
300	unsigned char hostc, errmask;
301
302	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
303	if (read_write == I2C_SMBUS_WRITE) {
304	/* set I2C_EN bit in configuration register */
305	pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
306	pci_write_config_byte(I801_dev, SMBHSTCFG,
307	hostc \| SMBHSTCFG_I2C_EN);
308	} else if (!isich5) {
309	dev_err(I801_dev,
310	"I2C_SMBUS_I2C_BLOCK_READ unsupported!\n");
311	return -1;
312	}
313	}
314
315	if (read_write == I2C_SMBUS_WRITE) {
316	len = data->block[0];
317	if (len < 1)
318	len = 1;
319	if (len > 32)
320	len = 32;
321	outb_p(len, SMBHSTDAT0);
322	outb_p(data->block[1], SMBBLKDAT);
323	} else {
324	len = 32; /* max for reads */
325	}
326
327	if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
328	/* set 32 byte buffer */
329	}
330
331	for (i = 1; i <= len; i++) {
332	if (i == len && read_write == I2C_SMBUS_READ)
333	smbcmd = I801_BLOCK_LAST;
334	else if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
335	read_write == I2C_SMBUS_READ)
336	smbcmd = I801_I2C_BLOCK_DATA;
337	else
338	smbcmd = I801_BLOCK_DATA;
339	outb_p(smbcmd \| ENABLE_INT9, SMBHSTCNT);
340
341	dev_dbg(I801_dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
342	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
343	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
344	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
345
346	/* Make sure the SMBus host is ready to start transmitting */
347	temp = inb_p(SMBHSTSTS);
348	if (i == 1) {
349	/* Erronenous conditions before transaction:
350	* Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
351	errmask=0x9f;
352	} else {
353	/* Erronenous conditions during transaction:
354	* Failed, Bus_Err, Dev_Err, Intr */
355	errmask=0x1e;
356	}
357	if (temp & errmask) {
358	dev_dbg(I801_dev, "SMBus busy (%02x). "
359	"Resetting... \n", temp);
360	outb_p(temp, SMBHSTSTS);
361	if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
362	dev_err(I801_dev,
363	"Reset failed! (%02x)\n", temp);
364	result = -1;
365	goto END;
366	}
367	if (i != 1) {
368	/* if die in middle of block transaction, fail */
369	result = -1;
370	goto END;
371	}
372	}
373
374	if (i == 1)
375	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
376
377	/* We will always wait for a fraction of a second! */
378	timeout = 0;
379	do {
380	temp = inb_p(SMBHSTSTS);
381	i2c_delay(1);
382	}
383	while ((!(temp & 0x80))
384	&& (timeout++ < MAX_TIMEOUT));
385
386	/* If the SMBus is still busy, we give up */
387	if (timeout >= MAX_TIMEOUT) {
388	result = -1;
389	dev_dbg(I801_dev, "SMBus Timeout!\n");
390	}
391
392	if (temp & 0x10) {
393	result = -1;
394	dev_dbg(I801_dev,
395	"Error: Failed bus transaction\n");
396	} else if (temp & 0x08) {
397	result = -1;
398	dev_err(I801_dev, "Bus collision!\n");
399	} else if (temp & 0x04) {
400	result = -1;
401	dev_dbg(I801_dev, "Error: no response!\n");
402	}
403
404	if (i == 1 && read_write == I2C_SMBUS_READ) {
405	if (command != I2C_SMBUS_I2C_BLOCK_DATA) {
406	len = inb_p(SMBHSTDAT0);
407	if (len < 1)
408	len = 1;
409	if (len > 32)
410	len = 32;
411	data->block[0] = len;
412	} else {
413	/* if slave returns < 32 bytes transaction will fail */
414	data->block[0] = 32;
415	}
416	}
417
418	/* Retrieve/store value in SMBBLKDAT */
419	if (read_write == I2C_SMBUS_READ)
420	data->block[i] = inb_p(SMBBLKDAT);
421	if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
422	outb_p(data->block[i+1], SMBBLKDAT);
423	if ((temp & 0x9e) != 0x00)
424	outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
425
426	if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
427	dev_dbg(I801_dev,
428	"Bad status (%02x) at end of transaction\n",
429	temp);
430	}
431	dev_dbg(I801_dev, "Block (post %d): CNT=%02x, CMD=%02x, "
432	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
433	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
434	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
435
436	if (result < 0)
437	goto END;
438	}
439
440	#ifdef HAVE_PEC
441	if(isich4 && command == I2C_SMBUS_BLOCK_DATA_PEC) {
442	/* wait for INTR bit as advised by Intel */
443	timeout = 0;
444	do {
445	temp = inb_p(SMBHSTSTS);
446	i2c_delay(1);
447	} while ((!(temp & 0x02))
448	&& (timeout++ < MAX_TIMEOUT));
449
450	if (timeout >= MAX_TIMEOUT) {
451	dev_dbg(I801_dev, "PEC Timeout!\n");
452	}
453	outb_p(temp, SMBHSTSTS);
454	}
455	#endif
456	result = 0;
457	END:
458	if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
459	read_write == I2C_SMBUS_WRITE) {
460	/* restore saved configuration register value */
461	pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
462	}
463	return result;
464	}
465
466	/* Return -1 on error. */
467	static s32 i801_access(struct i2c_adapter * adap, u16 addr,
468	unsigned short flags, char read_write, u8 command,
469	int size, union i2c_smbus_data * data)
470	{
471	int hwpec = 0;
472	int block = 0;
473	int ret, xact = 0;
474
475	#ifdef HAVE_PEC
476	if(isich4)
477	hwpec = (flags & I2C_CLIENT_PEC) != 0;
478	#endif
479
480	switch (size) {
481	case I2C_SMBUS_QUICK:
482	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
483	SMBHSTADD);
484	xact = I801_QUICK;
485	break;
486	case I2C_SMBUS_BYTE:
487	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
488	SMBHSTADD);
489	if (read_write == I2C_SMBUS_WRITE)
490	outb_p(command, SMBHSTCMD);
491	xact = I801_BYTE;
492	break;
493	case I2C_SMBUS_BYTE_DATA:
494	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
495	SMBHSTADD);
496	outb_p(command, SMBHSTCMD);
497	if (read_write == I2C_SMBUS_WRITE)
498	outb_p(data->byte, SMBHSTDAT0);
499	xact = I801_BYTE_DATA;
500	break;
501	case I2C_SMBUS_WORD_DATA:
502	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
503	SMBHSTADD);
504	outb_p(command, SMBHSTCMD);
505	if (read_write == I2C_SMBUS_WRITE) {
506	outb_p(data->word & 0xff, SMBHSTDAT0);
507	outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
508	}
509	xact = I801_WORD_DATA;
510	break;
511	case I2C_SMBUS_BLOCK_DATA:
512	case I2C_SMBUS_I2C_BLOCK_DATA:
513	#ifdef HAVE_PEC
514	case I2C_SMBUS_BLOCK_DATA_PEC:
515	if(hwpec && size == I2C_SMBUS_BLOCK_DATA)
516	size = I2C_SMBUS_BLOCK_DATA_PEC;
517	#endif
518	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
519	SMBHSTADD);
520	outb_p(command, SMBHSTCMD);
521	block = 1;
522	break;
523	case I2C_SMBUS_PROC_CALL:
524	default:
525	dev_err(I801_dev, "Unsupported transaction %d\n", size);
526	return -1;
527	}
528
529	#ifdef HAVE_PEC
530	if(isich4 && hwpec) {
531	if(size != I2C_SMBUS_QUICK &&
532	size != I2C_SMBUS_I2C_BLOCK_DATA)
533	outb_p(1, SMBAUXCTL); /* enable HW PEC */
534	}
535	#endif
536	if(block)
537	ret = i801_block_transaction(data, read_write, size);
538	else {
539	outb_p(xact \| ENABLE_INT9, SMBHSTCNT);
540	ret = i801_transaction();
541	}
542
543	#ifdef HAVE_PEC
544	if(isich4 && hwpec) {
545	if(size != I2C_SMBUS_QUICK &&
546	size != I2C_SMBUS_I2C_BLOCK_DATA)
547	outb_p(0, SMBAUXCTL);
548	}
549	#endif
550
551	if(block)
552	return ret;
553	if(ret)
554	return -1;
555	if ((read_write == I2C_SMBUS_WRITE) \|\| (xact == I801_QUICK))
556	return 0;
557
558	switch (xact & 0x7f) {
559	case I801_BYTE: /* Result put in SMBHSTDAT0 */
560	case I801_BYTE_DATA:
561	data->byte = inb_p(SMBHSTDAT0);
562	break;
563	case I801_WORD_DATA:
564	data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
565	break;
566	}
567	return 0;
568	}
569
570	static void i801_inc(struct i2c_adapter *adapter)
571	{
572	#ifdef MODULE
573	MOD_INC_USE_COUNT;
574	#endif
575	}
576
577	static void i801_dec(struct i2c_adapter *adapter)
578	{
579	#ifdef MODULE
580	MOD_DEC_USE_COUNT;
581	#endif
582	}
583
584	static u32 i801_func(struct i2c_adapter *adapter)
585	{
586	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
587	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
588	I2C_FUNC_SMBUS_BLOCK_DATA \| I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
589	#ifdef HAVE_PEC
590	\| (isich4 ? I2C_FUNC_SMBUS_BLOCK_DATA_PEC \|
591	I2C_FUNC_SMBUS_HWPEC_CALC
592	: 0)
593	#endif
594	#if 0
595	\| (isich5 ? I2C_FUNC_SMBUS_READ_I2C_BLOCK
596	: 0)
597	#endif
598	;
599	}
600
601	static struct i2c_algorithm smbus_algorithm = {
602	.name = "Non-I2C SMBus adapter",
603	.id = I2C_ALGO_SMBUS,
604	.smbus_xfer = i801_access,
605	.functionality = i801_func,
606	};
607
608	static struct i2c_adapter i801_adapter = {
609	.id = I2C_ALGO_SMBUS \| I2C_HW_SMBUS_I801,
610	.algo = &smbus_algorithm,
611	.name = "unset",
612	.inc_use = i801_inc,
613	.dec_use = i801_dec,
614	};
615
616	static struct pci_device_id i801_ids[] __devinitdata = {
617	{
618	.vendor = PCI_VENDOR_ID_INTEL,
619	.device = PCI_DEVICE_ID_INTEL_82801AA_3,
620	.subvendor = PCI_ANY_ID,
621	.subdevice = PCI_ANY_ID,
622	},
623	{
624	.vendor = PCI_VENDOR_ID_INTEL,
625	.device = PCI_DEVICE_ID_INTEL_82801AB_3,
626	.subvendor = PCI_ANY_ID,
627	.subdevice = PCI_ANY_ID,
628	},
629	{
630	.vendor = PCI_VENDOR_ID_INTEL,
631	.device = PCI_DEVICE_ID_INTEL_82801BA_2,
632	.subvendor = PCI_ANY_ID,
633	.subdevice = PCI_ANY_ID,
634	},
635	{
636	.vendor = PCI_VENDOR_ID_INTEL,
637	.device = PCI_DEVICE_ID_INTEL_82801CA_3,
638	.subvendor = PCI_ANY_ID,
639	.subdevice = PCI_ANY_ID,
640	},
641	{
642	.vendor = PCI_VENDOR_ID_INTEL,
643	.device = PCI_DEVICE_ID_INTEL_82801DB_3,
644	.subvendor = PCI_ANY_ID,
645	.subdevice = PCI_ANY_ID,
646	},
647	{
648	.vendor = PCI_VENDOR_ID_INTEL,
649	.device = PCI_DEVICE_ID_INTEL_82801EB_3,
650	.subvendor = PCI_ANY_ID,
651	.subdevice = PCI_ANY_ID,
652	},
653	{
654	.vendor = PCI_VENDOR_ID_INTEL,
655	.device = PCI_DEVICE_ID_INTEL_ESB_4,
656	.subvendor = PCI_ANY_ID,
657	.subdevice = PCI_ANY_ID,
658	},
659	{
660	.vendor = PCI_VENDOR_ID_INTEL,
661	.device = PCI_DEVICE_ID_INTEL_ICH6_16,
662	.subvendor = PCI_ANY_ID,
663	.subdevice = PCI_ANY_ID,
664	},
665	{
666	.vendor = PCI_VENDOR_ID_INTEL,
667	.device = PCI_DEVICE_ID_INTEL_ICH7_17,
668	.subvendor = PCI_ANY_ID,
669	.subdevice = PCI_ANY_ID,
670	},
671	{ 0, }
672	};
673
674	static int __devinit i801_probe(struct pci_dev dev, const struct pci_device_id id)
675	{
676
677	if (i801_setup(dev)) {
678	dev_warn(dev,
679	"I801 not detected, module not inserted.\n");
680	return -ENODEV;
681	}
682
683	snprintf(i801_adapter.name, 32,
684	"SMBus I801 adapter at %04x", i801_smba);
685	return i2c_add_adapter(&i801_adapter);
686	}
687
688	static void __devexit i801_remove(struct pci_dev *dev)
689	{
690	i2c_del_adapter(&i801_adapter);
691	release_region(i801_smba, (isich4 ? 16 : 8));
692	}
693
694	static struct pci_driver i801_driver = {
695	.name = "i801 smbus",
696	.id_table = i801_ids,
697	.probe = i801_probe,
698	.remove = __devexit_p(i801_remove),
699	};
700
701	static int __init i2c_i801_init(void)
702	{
703	printk(KERN_INFO "i2c-i801 version %s (%s)\n", LM_VERSION, LM_DATE);
704	return pci_module_init(&i801_driver);
705	}
706
707	static void __exit i2c_i801_exit(void)
708	{
709	pci_unregister_driver(&i801_driver);
710	}
711
712	MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
713	"Philip Edelbrock <phil@netroedge.com>, "
714	"and Mark D. Studebaker <mdsxyz123@yahoo.com>");
715	MODULE_DESCRIPTION("I801 SMBus driver");
716	MODULE_LICENSE("GPL");
717
718	module_init(i2c_i801_init);
719	module_exit(i2c_i801_exit);

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