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i2c-i801.c @ 2813

Revision 2813, 18.4 KB (checked in by khali, 8 years ago)
Use more PCI ID defines instead of numerical values.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`

Line
1	/*
2	i801.c - Part of lm_sensors, Linux kernel modules for hardware
3	monitoring
4	Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5	Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
6	<mdsxyz123@yahoo.com>
7
8	This program is free software; you can redistribute it and/or modify
9	it under the terms of the GNU General Public License as published by
10	the Free Software Foundation; either version 2 of the License, or
11	(at your option) any later version.
12
13	This program is distributed in the hope that it will be useful,
14	but WITHOUT ANY WARRANTY; without even the implied warranty of
15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	GNU General Public License for more details.
17
18	You should have received a copy of the GNU General Public License
19	along with this program; if not, write to the Free Software
20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21	*/
22
23	/*
24	SUPPORTED DEVICES PCI ID
25	82801AA 2413
26	82801AB 2423
27	82801BA 2443
28	82801CA/CAM 2483
29	82801DB 24C3 (HW PEC supported, 32 byte buffer not supported)
30	82801EB 24D3 (HW PEC supported, 32 byte buffer not supported)
31	6300ESB 25A4 ("")
32	ICH6 266A ("")
33	ICH7 27DA ("")
34	This driver supports several versions of Intel's I/O Controller Hubs (ICH).
35	For SMBus support, they are similar to the PIIX4 and are part
36	of Intel's '810' and other chipsets.
37	See the doc/busses/i2c-i801 file for details.
38	I2C Block Read supported for ICH5 and higher.
39	Block Process Call are not supported.
40	*/
41
42	/* Note: we assume there can only be one I801, with one SMBus interface */
43
44	/* #define DEBUG 1 */
45
46	#include <linux/module.h>
47	#include <linux/pci.h>
48	#include <linux/kernel.h>
49	#include <linux/stddef.h>
50	#include <linux/sched.h>
51	#include <linux/ioport.h>
52	#include <linux/init.h>
53	#include <linux/i2c.h>
54	#include <asm/io.h>
55	#include "version.h"
56	#include "sensors_compat.h"
57
58	/* 82801CA is undefined before kernel 2.4.13 */
59	#ifndef PCI_DEVICE_ID_INTEL_82801CA_3
60	#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483
61	#endif
62
63	/* 82801DB is undefined before kernel 2.4.19 */
64	#ifndef PCI_DEVICE_ID_INTEL_82801DB_3
65	#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3
66	#endif
67
68	/* 82801EB is undefined before kernel 2.4.21 */
69	#ifndef PCI_DEVICE_ID_INTEL_82801EB_3
70	#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3
71	#endif
72
73	/* ESB is undefined before kernel 2.4.22 */
74	#ifndef PCI_DEVICE_ID_INTEL_ESB_4
75	#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4
76	#endif
77
78	/* ICH6 is undefined */
79	#ifndef PCI_DEVICE_ID_INTEL_ICH6_16
80	#define PCI_DEVICE_ID_INTEL_ICH6_16 0x266a
81	#endif
82
83	#ifdef I2C_FUNC_SMBUS_BLOCK_DATA_PEC
84	#define HAVE_PEC
85	#endif
86
87	/* I801 SMBus address offsets */
88	#define SMBHSTSTS (0 + i801_smba)
89	#define SMBHSTCNT (2 + i801_smba)
90	#define SMBHSTCMD (3 + i801_smba)
91	#define SMBHSTADD (4 + i801_smba)
92	#define SMBHSTDAT0 (5 + i801_smba)
93	#define SMBHSTDAT1 (6 + i801_smba)
94	#define SMBBLKDAT (7 + i801_smba)
95	#define SMBPEC (8 + i801_smba) /* ICH4 only */
96	#define SMBAUXSTS (12 + i801_smba) /* ICH4 only */
97	#define SMBAUXCTL (13 + i801_smba) /* ICH4 only */
98
99	/* PCI Address Constants */
100	#define SMBBA 0x020
101	#define SMBHSTCFG 0x040
102	#define SMBREV 0x008
103
104	/* Host configuration bits for SMBHSTCFG */
105	#define SMBHSTCFG_HST_EN 1
106	#define SMBHSTCFG_SMB_SMI_EN 2
107	#define SMBHSTCFG_I2C_EN 4
108
109	/* Other settings */
110	#define MAX_TIMEOUT 100
111	#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
112
113	/* I801 command constants */
114	#define I801_QUICK 0x00
115	#define I801_BYTE 0x04
116	#define I801_BYTE_DATA 0x08
117	#define I801_WORD_DATA 0x0C
118	#define I801_PROC_CALL 0x10 /* later chips only, unimplemented */
119	#define I801_BLOCK_DATA 0x14
120	#define I801_I2C_BLOCK_DATA 0x18 /* ich4 and later */
121	#define I801_BLOCK_LAST 0x34
122	#define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */
123	#define I801_START 0x40
124	#define I801_PEC_EN 0x80 /* ich4 and later */
125
126	/* insmod parameters */
127
128	/* If force_addr is set to anything different from 0, we forcibly enable
129	the I801 at the given address. VERY DANGEROUS! */
130	static int force_addr = 0;
131	MODULE_PARM(force_addr, "i");
132	MODULE_PARM_DESC(force_addr,
133	"Forcibly enable the I801 at the given address. "
134	"EXTREMELY DANGEROUS!");
135
136	static int i801_transaction(void);
137	static int i801_block_transaction(union i2c_smbus_data *data,
138	char read_write, int command);
139
140	static unsigned short i801_smba;
141	static struct pci_dev *I801_dev;
142	static int isich4; /* is PEC supported? */
143	static int isich5; /* is i2c block read supported? */
144
145	static int i801_setup(struct pci_dev *dev)
146	{
147	int error_return = 0;
148	unsigned char temp;
149
150	/* Note: we keep on searching until we have found 'function 3' */
151	if(PCI_FUNC(dev->devfn) != 3)
152	return -ENODEV;
153
154	I801_dev = dev;
155	if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_3 \|\|
156	dev->device == PCI_DEVICE_ID_INTEL_82801EB_3 \|\|
157	dev->device == PCI_DEVICE_ID_INTEL_ESB_4 \|\|
158	dev->device == PCI_DEVICE_ID_INTEL_ICH6_16 \|\|
159	dev->device == 0x27da)
160	isich4 = 1;
161	else
162	isich4 = 0;
163	isich5 = isich4 && dev->device != PCI_DEVICE_ID_INTEL_82801DB_3;
164
165	/* Determine the address of the SMBus areas */
166	if (force_addr) {
167	i801_smba = force_addr & 0xfff0;
168	} else {
169	pci_read_config_word(I801_dev, SMBBA, &i801_smba);
170	i801_smba &= 0xfff0;
171	if(i801_smba == 0) {
172	dev_err(dev, "SMB base address uninitialized"
173	"- upgrade BIOS or use force_addr=0xaddr\n");
174	return -ENODEV;
175	}
176	}
177
178	if (!request_region(i801_smba, (isich4 ? 16 : 8), "i801-smbus")) {
179	dev_err(dev, "I801_smb region 0x%x already in use!\n",
180	i801_smba);
181	error_return = -EBUSY;
182	goto END;
183	}
184
185	pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
186	temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
187	pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
188
189	/* If force_addr is set, we program the new address here. Just to make
190	sure, we disable the device first. */
191	if (force_addr) {
192	pci_write_config_byte(I801_dev, SMBHSTCFG, temp & 0xfe);
193	pci_write_config_word(I801_dev, SMBBA, i801_smba);
194	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 0x01);
195	dev_warn(dev, "WARNING: I801 SMBus interface set to "
196	"new address %04x!\n", i801_smba);
197	} else if ((temp & 1) == 0) {
198	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 1);
199	dev_warn(dev, "enabling SMBus device\n");
200	}
201
202	if (temp & 0x02)
203	dev_dbg(dev, "I801 using Interrupt SMI# for SMBus.\n");
204	else
205	dev_dbg(dev, "I801 using PCI Interrupt for SMBus.\n");
206
207	pci_read_config_byte(I801_dev, SMBREV, &temp);
208	dev_dbg(dev, "SMBREV = 0x%X\n", temp);
209	dev_dbg(dev, "I801_smba = 0x%X\n", i801_smba);
210
211	END:
212	return error_return;
213	}
214
215
216	static int i801_transaction(void)
217	{
218	int temp;
219	int result = 0;
220	int timeout = 0;
221
222	dev_dbg(I801_dev, "Transaction (pre): CNT=%02x, CMD=%02x,"
223	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
224	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
225	inb_p(SMBHSTDAT1));
226
227	/* Make sure the SMBus host is ready to start transmitting */
228	/* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
229	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
230	dev_dbg(I801_dev, "SMBus busy (%02x). Resetting... \n",
231	temp);
232	outb_p(temp, SMBHSTSTS);
233	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
234	dev_dbg(I801_dev, "Failed! (%02x)\n", temp);
235	return -1;
236	} else {
237	dev_dbg(I801_dev, "Successfull!\n");
238	}
239	}
240
241	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
242
243	/* We will always wait for a fraction of a second! */
244	do {
245	i2c_delay(1);
246	temp = inb_p(SMBHSTSTS);
247	} while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
248
249	/* If the SMBus is still busy, we give up */
250	if (timeout >= MAX_TIMEOUT) {
251	dev_dbg(I801_dev, "SMBus Timeout!\n");
252	result = -1;
253	}
254
255	if (temp & 0x10) {
256	result = -1;
257	dev_dbg(I801_dev, "Error: Failed bus transaction\n");
258	}
259
260	if (temp & 0x08) {
261	result = -1;
262	dev_err(I801_dev, "Bus collision! SMBus may be locked "
263	"until next hard reset. (sorry!)\n");
264	/* Clock stops and slave is stuck in mid-transmission */
265	}
266
267	if (temp & 0x04) {
268	result = -1;
269	dev_dbg(I801_dev, "Error: no response!\n");
270	}
271
272	if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
273	outb_p(inb(SMBHSTSTS), SMBHSTSTS);
274
275	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
276	dev_dbg(I801_dev, "Failed reset at end of transaction"
277	"(%02x)\n", temp);
278	}
279	dev_dbg(I801_dev, "Transaction (post): CNT=%02x, CMD=%02x, "
280	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
281	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
282	inb_p(SMBHSTDAT1));
283	return result;
284	}
285
286	/* All-inclusive block transaction function */
287	static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
288	int command)
289	{
290	int i, len;
291	int smbcmd;
292	int temp;
293	int result = 0;
294	int timeout;
295	unsigned char hostc, errmask;
296
297	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
298	if (read_write == I2C_SMBUS_WRITE) {
299	/* set I2C_EN bit in configuration register */
300	pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
301	pci_write_config_byte(I801_dev, SMBHSTCFG,
302	hostc \| SMBHSTCFG_I2C_EN);
303	} else if (!isich5) {
304	dev_err(I801_dev,
305	"I2C_SMBUS_I2C_BLOCK_READ unsupported!\n");
306	return -1;
307	}
308	}
309
310	if (read_write == I2C_SMBUS_WRITE) {
311	len = data->block[0];
312	if (len < 1)
313	len = 1;
314	if (len > 32)
315	len = 32;
316	outb_p(len, SMBHSTDAT0);
317	outb_p(data->block[1], SMBBLKDAT);
318	} else {
319	len = 32; /* max for reads */
320	}
321
322	if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
323	/* set 32 byte buffer */
324	}
325
326	for (i = 1; i <= len; i++) {
327	if (i == len && read_write == I2C_SMBUS_READ)
328	smbcmd = I801_BLOCK_LAST;
329	else if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
330	read_write == I2C_SMBUS_READ)
331	smbcmd = I801_I2C_BLOCK_DATA;
332	else
333	smbcmd = I801_BLOCK_DATA;
334	outb_p(smbcmd \| ENABLE_INT9, SMBHSTCNT);
335
336	dev_dbg(I801_dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
337	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
338	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
339	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
340
341	/* Make sure the SMBus host is ready to start transmitting */
342	temp = inb_p(SMBHSTSTS);
343	if (i == 1) {
344	/* Erronenous conditions before transaction:
345	* Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
346	errmask=0x9f;
347	} else {
348	/* Erronenous conditions during transaction:
349	* Failed, Bus_Err, Dev_Err, Intr */
350	errmask=0x1e;
351	}
352	if (temp & errmask) {
353	dev_dbg(I801_dev, "SMBus busy (%02x). "
354	"Resetting... \n", temp);
355	outb_p(temp, SMBHSTSTS);
356	if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
357	dev_err(I801_dev,
358	"Reset failed! (%02x)\n", temp);
359	result = -1;
360	goto END;
361	}
362	if (i != 1) {
363	/* if die in middle of block transaction, fail */
364	result = -1;
365	goto END;
366	}
367	}
368
369	if (i == 1)
370	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
371
372	/* We will always wait for a fraction of a second! */
373	timeout = 0;
374	do {
375	temp = inb_p(SMBHSTSTS);
376	i2c_delay(1);
377	}
378	while ((!(temp & 0x80))
379	&& (timeout++ < MAX_TIMEOUT));
380
381	/* If the SMBus is still busy, we give up */
382	if (timeout >= MAX_TIMEOUT) {
383	result = -1;
384	dev_dbg(I801_dev, "SMBus Timeout!\n");
385	}
386
387	if (temp & 0x10) {
388	result = -1;
389	dev_dbg(I801_dev,
390	"Error: Failed bus transaction\n");
391	} else if (temp & 0x08) {
392	result = -1;
393	dev_err(I801_dev, "Bus collision!\n");
394	} else if (temp & 0x04) {
395	result = -1;
396	dev_dbg(I801_dev, "Error: no response!\n");
397	}
398
399	if (i == 1 && read_write == I2C_SMBUS_READ) {
400	if (command != I2C_SMBUS_I2C_BLOCK_DATA) {
401	len = inb_p(SMBHSTDAT0);
402	if (len < 1)
403	len = 1;
404	if (len > 32)
405	len = 32;
406	data->block[0] = len;
407	} else {
408	/* if slave returns < 32 bytes transaction will fail */
409	data->block[0] = 32;
410	}
411	}
412
413	/* Retrieve/store value in SMBBLKDAT */
414	if (read_write == I2C_SMBUS_READ)
415	data->block[i] = inb_p(SMBBLKDAT);
416	if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
417	outb_p(data->block[i+1], SMBBLKDAT);
418	if ((temp & 0x9e) != 0x00)
419	outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
420
421	if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
422	dev_dbg(I801_dev,
423	"Bad status (%02x) at end of transaction\n",
424	temp);
425	}
426	dev_dbg(I801_dev, "Block (post %d): CNT=%02x, CMD=%02x, "
427	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
428	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
429	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
430
431	if (result < 0)
432	goto END;
433	}
434
435	#ifdef HAVE_PEC
436	if(isich4 && command == I2C_SMBUS_BLOCK_DATA_PEC) {
437	/* wait for INTR bit as advised by Intel */
438	timeout = 0;
439	do {
440	temp = inb_p(SMBHSTSTS);
441	i2c_delay(1);
442	} while ((!(temp & 0x02))
443	&& (timeout++ < MAX_TIMEOUT));
444
445	if (timeout >= MAX_TIMEOUT) {
446	dev_dbg(I801_dev, "PEC Timeout!\n");
447	}
448	outb_p(temp, SMBHSTSTS);
449	}
450	#endif
451	result = 0;
452	END:
453	if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
454	read_write == I2C_SMBUS_WRITE) {
455	/* restore saved configuration register value */
456	pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
457	}
458	return result;
459	}
460
461	/* Return -1 on error. */
462	static s32 i801_access(struct i2c_adapter * adap, u16 addr,
463	unsigned short flags, char read_write, u8 command,
464	int size, union i2c_smbus_data * data)
465	{
466	int hwpec = 0;
467	int block = 0;
468	int ret, xact = 0;
469
470	#ifdef HAVE_PEC
471	if(isich4)
472	hwpec = (flags & I2C_CLIENT_PEC) != 0;
473	#endif
474
475	switch (size) {
476	case I2C_SMBUS_QUICK:
477	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
478	SMBHSTADD);
479	xact = I801_QUICK;
480	break;
481	case I2C_SMBUS_BYTE:
482	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
483	SMBHSTADD);
484	if (read_write == I2C_SMBUS_WRITE)
485	outb_p(command, SMBHSTCMD);
486	xact = I801_BYTE;
487	break;
488	case I2C_SMBUS_BYTE_DATA:
489	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
490	SMBHSTADD);
491	outb_p(command, SMBHSTCMD);
492	if (read_write == I2C_SMBUS_WRITE)
493	outb_p(data->byte, SMBHSTDAT0);
494	xact = I801_BYTE_DATA;
495	break;
496	case I2C_SMBUS_WORD_DATA:
497	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
498	SMBHSTADD);
499	outb_p(command, SMBHSTCMD);
500	if (read_write == I2C_SMBUS_WRITE) {
501	outb_p(data->word & 0xff, SMBHSTDAT0);
502	outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
503	}
504	xact = I801_WORD_DATA;
505	break;
506	case I2C_SMBUS_BLOCK_DATA:
507	case I2C_SMBUS_I2C_BLOCK_DATA:
508	#ifdef HAVE_PEC
509	case I2C_SMBUS_BLOCK_DATA_PEC:
510	if(hwpec && size == I2C_SMBUS_BLOCK_DATA)
511	size = I2C_SMBUS_BLOCK_DATA_PEC;
512	#endif
513	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
514	SMBHSTADD);
515	outb_p(command, SMBHSTCMD);
516	block = 1;
517	break;
518	case I2C_SMBUS_PROC_CALL:
519	default:
520	dev_err(I801_dev, "Unsupported transaction %d\n", size);
521	return -1;
522	}
523
524	#ifdef HAVE_PEC
525	if(isich4 && hwpec) {
526	if(size != I2C_SMBUS_QUICK &&
527	size != I2C_SMBUS_I2C_BLOCK_DATA)
528	outb_p(1, SMBAUXCTL); /* enable HW PEC */
529	}
530	#endif
531	if(block)
532	ret = i801_block_transaction(data, read_write, size);
533	else {
534	outb_p(xact \| ENABLE_INT9, SMBHSTCNT);
535	ret = i801_transaction();
536	}
537
538	#ifdef HAVE_PEC
539	if(isich4 && hwpec) {
540	if(size != I2C_SMBUS_QUICK &&
541	size != I2C_SMBUS_I2C_BLOCK_DATA)
542	outb_p(0, SMBAUXCTL);
543	}
544	#endif
545
546	if(block)
547	return ret;
548	if(ret)
549	return -1;
550	if ((read_write == I2C_SMBUS_WRITE) \|\| (xact == I801_QUICK))
551	return 0;
552
553	switch (xact & 0x7f) {
554	case I801_BYTE: /* Result put in SMBHSTDAT0 */
555	case I801_BYTE_DATA:
556	data->byte = inb_p(SMBHSTDAT0);
557	break;
558	case I801_WORD_DATA:
559	data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
560	break;
561	}
562	return 0;
563	}
564
565	static void i801_inc(struct i2c_adapter *adapter)
566	{
567	#ifdef MODULE
568	MOD_INC_USE_COUNT;
569	#endif
570	}
571
572	static void i801_dec(struct i2c_adapter *adapter)
573	{
574	#ifdef MODULE
575	MOD_DEC_USE_COUNT;
576	#endif
577	}
578
579	static u32 i801_func(struct i2c_adapter *adapter)
580	{
581	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
582	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
583	I2C_FUNC_SMBUS_BLOCK_DATA \| I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
584	#ifdef HAVE_PEC
585	\| (isich4 ? I2C_FUNC_SMBUS_BLOCK_DATA_PEC \|
586	I2C_FUNC_SMBUS_HWPEC_CALC
587	: 0)
588	#endif
589	\| (isich5 ? I2C_FUNC_SMBUS_READ_I2C_BLOCK
590	: 0)
591	;
592	}
593
594	static struct i2c_algorithm smbus_algorithm = {
595	.name = "Non-I2C SMBus adapter",
596	.id = I2C_ALGO_SMBUS,
597	.smbus_xfer = i801_access,
598	.functionality = i801_func,
599	};
600
601	static struct i2c_adapter i801_adapter = {
602	.id = I2C_ALGO_SMBUS \| I2C_HW_SMBUS_I801,
603	.algo = &smbus_algorithm,
604	.name = "unset",
605	.inc_use = i801_inc,
606	.dec_use = i801_dec,
607	};
608
609	static struct pci_device_id i801_ids[] __devinitdata = {
610	{
611	.vendor = PCI_VENDOR_ID_INTEL,
612	.device = PCI_DEVICE_ID_INTEL_82801AA_3,
613	.subvendor = PCI_ANY_ID,
614	.subdevice = PCI_ANY_ID,
615	},
616	{
617	.vendor = PCI_VENDOR_ID_INTEL,
618	.device = PCI_DEVICE_ID_INTEL_82801AB_3,
619	.subvendor = PCI_ANY_ID,
620	.subdevice = PCI_ANY_ID,
621	},
622	{
623	.vendor = PCI_VENDOR_ID_INTEL,
624	.device = PCI_DEVICE_ID_INTEL_82801BA_2,
625	.subvendor = PCI_ANY_ID,
626	.subdevice = PCI_ANY_ID,
627	},
628	{
629	.vendor = PCI_VENDOR_ID_INTEL,
630	.device = PCI_DEVICE_ID_INTEL_82801CA_3,
631	.subvendor = PCI_ANY_ID,
632	.subdevice = PCI_ANY_ID,
633	},
634	{
635	.vendor = PCI_VENDOR_ID_INTEL,
636	.device = PCI_DEVICE_ID_INTEL_82801DB_3,
637	.subvendor = PCI_ANY_ID,
638	.subdevice = PCI_ANY_ID,
639	},
640	{
641	.vendor = PCI_VENDOR_ID_INTEL,
642	.device = PCI_DEVICE_ID_INTEL_82801EB_3,
643	.subvendor = PCI_ANY_ID,
644	.subdevice = PCI_ANY_ID,
645	},
646	{
647	.vendor = PCI_VENDOR_ID_INTEL,
648	.device = PCI_DEVICE_ID_INTEL_ESB_4,
649	.subvendor = PCI_ANY_ID,
650	.subdevice = PCI_ANY_ID,
651	},
652	{
653	.vendor = PCI_VENDOR_ID_INTEL,
654	.device = PCI_DEVICE_ID_INTEL_ICH6_16,
655	.subvendor = PCI_ANY_ID,
656	.subdevice = PCI_ANY_ID,
657	},
658	{
659	.vendor = PCI_VENDOR_ID_INTEL,
660	.device = 0x27da, /* ICH7 */
661	.subvendor = PCI_ANY_ID,
662	.subdevice = PCI_ANY_ID,
663	},
664	{ 0, }
665	};
666
667	static int __devinit i801_probe(struct pci_dev dev, const struct pci_device_id id)
668	{
669
670	if (i801_setup(dev)) {
671	dev_warn(dev,
672	"I801 not detected, module not inserted.\n");
673	return -ENODEV;
674	}
675
676	snprintf(i801_adapter.name, 32,
677	"SMBus I801 adapter at %04x", i801_smba);
678	return i2c_add_adapter(&i801_adapter);
679	}
680
681	static void __devexit i801_remove(struct pci_dev *dev)
682	{
683	i2c_del_adapter(&i801_adapter);
684	release_region(i801_smba, (isich4 ? 16 : 8));
685	}
686
687	static struct pci_driver i801_driver = {
688	.name = "i801 smbus",
689	.id_table = i801_ids,
690	.probe = i801_probe,
691	.remove = __devexit_p(i801_remove),
692	};
693
694	static int __init i2c_i801_init(void)
695	{
696	printk(KERN_INFO "i2c-i801 version %s (%s)\n", LM_VERSION, LM_DATE);
697	return pci_module_init(&i801_driver);
698	}
699
700	static void __exit i2c_i801_exit(void)
701	{
702	pci_unregister_driver(&i801_driver);
703	}
704
705	MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
706	"Philip Edelbrock <phil@netroedge.com>, "
707	"and Mark D. Studebaker <mdsxyz123@yahoo.com>");
708	MODULE_DESCRIPTION("I801 SMBus driver");
709	MODULE_LICENSE("GPL");
710
711	module_init(i2c_i801_init);
712	module_exit(i2c_i801_exit);

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