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i2c-i801.c @ 2789

Revision 2789, 17.1 KB (checked in by mds, 8 years ago)
clarify i2c block read error message
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`

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1	/*
2	i801.c - Part of lm_sensors, Linux kernel modules for hardware
3	monitoring
4	Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5	Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
6	<mdsxyz123@yahoo.com>
7
8	This program is free software; you can redistribute it and/or modify
9	it under the terms of the GNU General Public License as published by
10	the Free Software Foundation; either version 2 of the License, or
11	(at your option) any later version.
12
13	This program is distributed in the hope that it will be useful,
14	but WITHOUT ANY WARRANTY; without even the implied warranty of
15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	GNU General Public License for more details.
17
18	You should have received a copy of the GNU General Public License
19	along with this program; if not, write to the Free Software
20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21	*/
22
23	/*
24	SUPPORTED DEVICES PCI ID
25	82801AA 2413
26	82801AB 2423
27	82801BA 2443
28	82801CA/CAM 2483
29	82801DB 24C3 (HW PEC supported, 32 byte buffer not supported)
30	82801EB 24D3 (HW PEC supported, 32 byte buffer not supported)
31	6300ESB 25A4 ("")
32	ICH6 266A
33	This driver supports several versions of Intel's I/O Controller Hubs (ICH).
34	For SMBus support, they are similar to the PIIX4 and are part
35	of Intel's '810' and other chipsets.
36	See the doc/busses/i2c-i801 file for details.
37	I2C Block Read and Process Call are not supported.
38	*/
39
40	/* Note: we assume there can only be one I801, with one SMBus interface */
41
42	/* #define DEBUG 1 */
43
44	#include <linux/module.h>
45	#include <linux/pci.h>
46	#include <linux/kernel.h>
47	#include <linux/stddef.h>
48	#include <linux/sched.h>
49	#include <linux/ioport.h>
50	#include <linux/init.h>
51	#include <linux/i2c.h>
52	#include <asm/io.h>
53	#include "version.h"
54	#include "sensors_compat.h"
55
56	/* 82801DB is undefined before kernel 2.4.19 */
57	#ifndef PCI_DEVICE_ID_INTEL_82801DB_3
58	#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3
59	#endif
60
61	#ifdef I2C_FUNC_SMBUS_BLOCK_DATA_PEC
62	#define HAVE_PEC
63	#endif
64
65	/* I801 SMBus address offsets */
66	#define SMBHSTSTS (0 + i801_smba)
67	#define SMBHSTCNT (2 + i801_smba)
68	#define SMBHSTCMD (3 + i801_smba)
69	#define SMBHSTADD (4 + i801_smba)
70	#define SMBHSTDAT0 (5 + i801_smba)
71	#define SMBHSTDAT1 (6 + i801_smba)
72	#define SMBBLKDAT (7 + i801_smba)
73	#define SMBPEC (8 + i801_smba) /* ICH4 only */
74	#define SMBAUXSTS (12 + i801_smba) /* ICH4 only */
75	#define SMBAUXCTL (13 + i801_smba) /* ICH4 only */
76
77	/* PCI Address Constants */
78	#define SMBBA 0x020
79	#define SMBHSTCFG 0x040
80	#define SMBREV 0x008
81
82	/* Host configuration bits for SMBHSTCFG */
83	#define SMBHSTCFG_HST_EN 1
84	#define SMBHSTCFG_SMB_SMI_EN 2
85	#define SMBHSTCFG_I2C_EN 4
86
87	/* Other settings */
88	#define MAX_TIMEOUT 100
89	#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
90
91	/* I801 command constants */
92	#define I801_QUICK 0x00
93	#define I801_BYTE 0x04
94	#define I801_BYTE_DATA 0x08
95	#define I801_WORD_DATA 0x0C
96	#define I801_PROC_CALL 0x10 /* later chips only, unimplemented */
97	#define I801_BLOCK_DATA 0x14
98	#define I801_I2C_BLOCK_DATA 0x18 /* unimplemented */
99	#define I801_BLOCK_LAST 0x34
100	#define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */
101	#define I801_START 0x40
102	#define I801_PEC_EN 0x80 /* ICH4 only */
103
104	/* insmod parameters */
105
106	/* If force_addr is set to anything different from 0, we forcibly enable
107	the I801 at the given address. VERY DANGEROUS! */
108	static int force_addr = 0;
109	MODULE_PARM(force_addr, "i");
110	MODULE_PARM_DESC(force_addr,
111	"Forcibly enable the I801 at the given address. "
112	"EXTREMELY DANGEROUS!");
113
114	static int i801_transaction(void);
115	static int i801_block_transaction(union i2c_smbus_data *data,
116	char read_write, int command);
117
118	static unsigned short i801_smba;
119	static struct pci_dev *I801_dev;
120	static int isich4;
121
122	static int i801_setup(struct pci_dev *dev)
123	{
124	int error_return = 0;
125	unsigned char temp;
126
127	/* Note: we keep on searching until we have found 'function 3' */
128	if(PCI_FUNC(dev->devfn) != 3)
129	return -ENODEV;
130
131	I801_dev = dev;
132	if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_3 \|\|
133	dev->device == 0x24d3 \|\|
134	dev->device == 0x25a4)
135	isich4 = 1;
136	else
137	isich4 = 0;
138
139	/* Determine the address of the SMBus areas */
140	if (force_addr) {
141	i801_smba = force_addr & 0xfff0;
142	} else {
143	pci_read_config_word(I801_dev, SMBBA, &i801_smba);
144	i801_smba &= 0xfff0;
145	if(i801_smba == 0) {
146	dev_err(dev, "SMB base address uninitialized"
147	"- upgrade BIOS or use force_addr=0xaddr\n");
148	return -ENODEV;
149	}
150	}
151
152	if (!request_region(i801_smba, (isich4 ? 16 : 8), "i801-smbus")) {
153	dev_err(dev, "I801_smb region 0x%x already in use!\n",
154	i801_smba);
155	error_return = -EBUSY;
156	goto END;
157	}
158
159	pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
160	temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
161	pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
162
163	/* If force_addr is set, we program the new address here. Just to make
164	sure, we disable the device first. */
165	if (force_addr) {
166	pci_write_config_byte(I801_dev, SMBHSTCFG, temp & 0xfe);
167	pci_write_config_word(I801_dev, SMBBA, i801_smba);
168	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 0x01);
169	dev_warn(dev, "WARNING: I801 SMBus interface set to "
170	"new address %04x!\n", i801_smba);
171	} else if ((temp & 1) == 0) {
172	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 1);
173	dev_warn(dev, "enabling SMBus device\n");
174	}
175
176	if (temp & 0x02)
177	dev_dbg(dev, "I801 using Interrupt SMI# for SMBus.\n");
178	else
179	dev_dbg(dev, "I801 using PCI Interrupt for SMBus.\n");
180
181	pci_read_config_byte(I801_dev, SMBREV, &temp);
182	dev_dbg(dev, "SMBREV = 0x%X\n", temp);
183	dev_dbg(dev, "I801_smba = 0x%X\n", i801_smba);
184
185	END:
186	return error_return;
187	}
188
189
190	static int i801_transaction(void)
191	{
192	int temp;
193	int result = 0;
194	int timeout = 0;
195
196	dev_dbg(I801_dev, "Transaction (pre): CNT=%02x, CMD=%02x,"
197	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
198	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
199	inb_p(SMBHSTDAT1));
200
201	/* Make sure the SMBus host is ready to start transmitting */
202	/* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
203	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
204	dev_dbg(I801_dev, "SMBus busy (%02x). Resetting... \n",
205	temp);
206	outb_p(temp, SMBHSTSTS);
207	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
208	dev_dbg(I801_dev, "Failed! (%02x)\n", temp);
209	return -1;
210	} else {
211	dev_dbg(I801_dev, "Successfull!\n");
212	}
213	}
214
215	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
216
217	/* We will always wait for a fraction of a second! */
218	do {
219	i2c_delay(1);
220	temp = inb_p(SMBHSTSTS);
221	} while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
222
223	/* If the SMBus is still busy, we give up */
224	if (timeout >= MAX_TIMEOUT) {
225	dev_dbg(I801_dev, "SMBus Timeout!\n");
226	result = -1;
227	}
228
229	if (temp & 0x10) {
230	result = -1;
231	dev_dbg(I801_dev, "Error: Failed bus transaction\n");
232	}
233
234	if (temp & 0x08) {
235	result = -1;
236	dev_err(I801_dev, "Bus collision! SMBus may be locked "
237	"until next hard reset. (sorry!)\n");
238	/* Clock stops and slave is stuck in mid-transmission */
239	}
240
241	if (temp & 0x04) {
242	result = -1;
243	dev_dbg(I801_dev, "Error: no response!\n");
244	}
245
246	if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
247	outb_p(inb(SMBHSTSTS), SMBHSTSTS);
248
249	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
250	dev_dbg(I801_dev, "Failed reset at end of transaction"
251	"(%02x)\n", temp);
252	}
253	dev_dbg(I801_dev, "Transaction (post): CNT=%02x, CMD=%02x, "
254	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
255	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
256	inb_p(SMBHSTDAT1));
257	return result;
258	}
259
260	/* All-inclusive block transaction function */
261	static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
262	int command)
263	{
264	int i, len;
265	int smbcmd;
266	int temp;
267	int result = 0;
268	int timeout;
269	unsigned char hostc, errmask;
270
271	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
272	if (read_write == I2C_SMBUS_WRITE) {
273	/* set I2C_EN bit in configuration register */
274	pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
275	pci_write_config_byte(I801_dev, SMBHSTCFG,
276	hostc \| SMBHSTCFG_I2C_EN);
277	} else {
278	dev_err(I801_dev,
279	"I2C_SMBUS_I2C_BLOCK_READ unsupported!\n");
280	return -1;
281	}
282	}
283
284	if (read_write == I2C_SMBUS_WRITE) {
285	len = data->block[0];
286	if (len < 1)
287	len = 1;
288	if (len > 32)
289	len = 32;
290	outb_p(len, SMBHSTDAT0);
291	outb_p(data->block[1], SMBBLKDAT);
292	} else {
293	len = 32; /* max for reads */
294	}
295
296	if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
297	/* set 32 byte buffer */
298	}
299
300	for (i = 1; i <= len; i++) {
301	if (i == len && read_write == I2C_SMBUS_READ)
302	smbcmd = I801_BLOCK_LAST;
303	else
304	smbcmd = I801_BLOCK_DATA;
305	outb_p(smbcmd \| ENABLE_INT9, SMBHSTCNT);
306
307	dev_dbg(I801_dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
308	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
309	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
310	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
311
312	/* Make sure the SMBus host is ready to start transmitting */
313	temp = inb_p(SMBHSTSTS);
314	if (i == 1) {
315	/* Erronenous conditions before transaction:
316	* Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
317	errmask=0x9f;
318	} else {
319	/* Erronenous conditions during transaction:
320	* Failed, Bus_Err, Dev_Err, Intr */
321	errmask=0x1e;
322	}
323	if (temp & errmask) {
324	dev_dbg(I801_dev, "SMBus busy (%02x). "
325	"Resetting... \n", temp);
326	outb_p(temp, SMBHSTSTS);
327	if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
328	dev_err(I801_dev,
329	"Reset failed! (%02x)\n", temp);
330	result = -1;
331	goto END;
332	}
333	if (i != 1) {
334	/* if die in middle of block transaction, fail */
335	result = -1;
336	goto END;
337	}
338	}
339
340	if (i == 1)
341	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
342
343	/* We will always wait for a fraction of a second! */
344	timeout = 0;
345	do {
346	temp = inb_p(SMBHSTSTS);
347	i2c_delay(1);
348	}
349	while ((!(temp & 0x80))
350	&& (timeout++ < MAX_TIMEOUT));
351
352	/* If the SMBus is still busy, we give up */
353	if (timeout >= MAX_TIMEOUT) {
354	result = -1;
355	dev_dbg(I801_dev, "SMBus Timeout!\n");
356	}
357
358	if (temp & 0x10) {
359	result = -1;
360	dev_dbg(I801_dev,
361	"Error: Failed bus transaction\n");
362	} else if (temp & 0x08) {
363	result = -1;
364	dev_err(I801_dev, "Bus collision!\n");
365	} else if (temp & 0x04) {
366	result = -1;
367	dev_dbg(I801_dev, "Error: no response!\n");
368	}
369
370	if (i == 1 && read_write == I2C_SMBUS_READ) {
371	len = inb_p(SMBHSTDAT0);
372	if (len < 1)
373	len = 1;
374	if (len > 32)
375	len = 32;
376	data->block[0] = len;
377	}
378
379	/* Retrieve/store value in SMBBLKDAT */
380	if (read_write == I2C_SMBUS_READ)
381	data->block[i] = inb_p(SMBBLKDAT);
382	if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
383	outb_p(data->block[i+1], SMBBLKDAT);
384	if ((temp & 0x9e) != 0x00)
385	outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
386
387	if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
388	dev_dbg(I801_dev,
389	"Bad status (%02x) at end of transaction\n",
390	temp);
391	}
392	dev_dbg(I801_dev, "Block (post %d): CNT=%02x, CMD=%02x, "
393	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
394	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
395	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
396
397	if (result < 0)
398	goto END;
399	}
400
401	#ifdef HAVE_PEC
402	if(isich4 && command == I2C_SMBUS_BLOCK_DATA_PEC) {
403	/* wait for INTR bit as advised by Intel */
404	timeout = 0;
405	do {
406	temp = inb_p(SMBHSTSTS);
407	i2c_delay(1);
408	} while ((!(temp & 0x02))
409	&& (timeout++ < MAX_TIMEOUT));
410
411	if (timeout >= MAX_TIMEOUT) {
412	dev_dbg(I801_dev, "PEC Timeout!\n");
413	}
414	outb_p(temp, SMBHSTSTS);
415	}
416	#endif
417	result = 0;
418	END:
419	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
420	/* restore saved configuration register value */
421	pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
422	}
423	return result;
424	}
425
426	/* Return -1 on error. */
427	static s32 i801_access(struct i2c_adapter * adap, u16 addr,
428	unsigned short flags, char read_write, u8 command,
429	int size, union i2c_smbus_data * data)
430	{
431	int hwpec = 0;
432	int block = 0;
433	int ret, xact = 0;
434
435	#ifdef HAVE_PEC
436	if(isich4)
437	hwpec = (flags & I2C_CLIENT_PEC) != 0;
438	#endif
439
440	switch (size) {
441	case I2C_SMBUS_QUICK:
442	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
443	SMBHSTADD);
444	xact = I801_QUICK;
445	break;
446	case I2C_SMBUS_BYTE:
447	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
448	SMBHSTADD);
449	if (read_write == I2C_SMBUS_WRITE)
450	outb_p(command, SMBHSTCMD);
451	xact = I801_BYTE;
452	break;
453	case I2C_SMBUS_BYTE_DATA:
454	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
455	SMBHSTADD);
456	outb_p(command, SMBHSTCMD);
457	if (read_write == I2C_SMBUS_WRITE)
458	outb_p(data->byte, SMBHSTDAT0);
459	xact = I801_BYTE_DATA;
460	break;
461	case I2C_SMBUS_WORD_DATA:
462	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
463	SMBHSTADD);
464	outb_p(command, SMBHSTCMD);
465	if (read_write == I2C_SMBUS_WRITE) {
466	outb_p(data->word & 0xff, SMBHSTDAT0);
467	outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
468	}
469	xact = I801_WORD_DATA;
470	break;
471	case I2C_SMBUS_BLOCK_DATA:
472	case I2C_SMBUS_I2C_BLOCK_DATA:
473	#ifdef HAVE_PEC
474	case I2C_SMBUS_BLOCK_DATA_PEC:
475	if(hwpec && size == I2C_SMBUS_BLOCK_DATA)
476	size = I2C_SMBUS_BLOCK_DATA_PEC;
477	#endif
478	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
479	SMBHSTADD);
480	outb_p(command, SMBHSTCMD);
481	block = 1;
482	break;
483	case I2C_SMBUS_PROC_CALL:
484	default:
485	dev_err(I801_dev, "Unsupported transaction %d\n", size);
486	return -1;
487	}
488
489	#ifdef HAVE_PEC
490	if(isich4 && hwpec) {
491	if(size != I2C_SMBUS_QUICK &&
492	size != I2C_SMBUS_I2C_BLOCK_DATA)
493	outb_p(1, SMBAUXCTL); /* enable HW PEC */
494	}
495	#endif
496	if(block)
497	ret = i801_block_transaction(data, read_write, size);
498	else {
499	outb_p(xact \| ENABLE_INT9, SMBHSTCNT);
500	ret = i801_transaction();
501	}
502
503	#ifdef HAVE_PEC
504	if(isich4 && hwpec) {
505	if(size != I2C_SMBUS_QUICK &&
506	size != I2C_SMBUS_I2C_BLOCK_DATA)
507	outb_p(0, SMBAUXCTL);
508	}
509	#endif
510
511	if(block)
512	return ret;
513	if(ret)
514	return -1;
515	if ((read_write == I2C_SMBUS_WRITE) \|\| (xact == I801_QUICK))
516	return 0;
517
518	switch (xact & 0x7f) {
519	case I801_BYTE: /* Result put in SMBHSTDAT0 */
520	case I801_BYTE_DATA:
521	data->byte = inb_p(SMBHSTDAT0);
522	break;
523	case I801_WORD_DATA:
524	data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
525	break;
526	}
527	return 0;
528	}
529
530	static void i801_inc(struct i2c_adapter *adapter)
531	{
532	#ifdef MODULE
533	MOD_INC_USE_COUNT;
534	#endif
535	}
536
537	static void i801_dec(struct i2c_adapter *adapter)
538	{
539	#ifdef MODULE
540	MOD_DEC_USE_COUNT;
541	#endif
542	}
543
544	static u32 i801_func(struct i2c_adapter *adapter)
545	{
546	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
547	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
548	I2C_FUNC_SMBUS_BLOCK_DATA \| I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
549	#ifdef HAVE_PEC
550	\| (isich4 ? I2C_FUNC_SMBUS_BLOCK_DATA_PEC \|
551	I2C_FUNC_SMBUS_HWPEC_CALC
552	: 0)
553	#endif
554	;
555	}
556
557	static struct i2c_algorithm smbus_algorithm = {
558	.name = "Non-I2C SMBus adapter",
559	.id = I2C_ALGO_SMBUS,
560	.smbus_xfer = i801_access,
561	.functionality = i801_func,
562	};
563
564	static struct i2c_adapter i801_adapter = {
565	.id = I2C_ALGO_SMBUS \| I2C_HW_SMBUS_I801,
566	.algo = &smbus_algorithm,
567	.name = "unset",
568	.inc_use = i801_inc,
569	.dec_use = i801_dec,
570	};
571
572	static struct pci_device_id i801_ids[] __devinitdata = {
573	{
574	.vendor = PCI_VENDOR_ID_INTEL,
575	.device = PCI_DEVICE_ID_INTEL_82801AA_3,
576	.subvendor = PCI_ANY_ID,
577	.subdevice = PCI_ANY_ID,
578	},
579	{
580	.vendor = PCI_VENDOR_ID_INTEL,
581	.device = PCI_DEVICE_ID_INTEL_82801AB_3,
582	.subvendor = PCI_ANY_ID,
583	.subdevice = PCI_ANY_ID,
584	},
585	{
586	.vendor = PCI_VENDOR_ID_INTEL,
587	.device = PCI_DEVICE_ID_INTEL_82801BA_2,
588	.subvendor = PCI_ANY_ID,
589	.subdevice = PCI_ANY_ID,
590	},
591	{
592	.vendor = PCI_VENDOR_ID_INTEL,
593	.device = PCI_DEVICE_ID_INTEL_82801CA_3,
594	.subvendor = PCI_ANY_ID,
595	.subdevice = PCI_ANY_ID,
596	},
597	{
598	.vendor = PCI_VENDOR_ID_INTEL,
599	.device = PCI_DEVICE_ID_INTEL_82801DB_3,
600	.subvendor = PCI_ANY_ID,
601	.subdevice = PCI_ANY_ID,
602	},
603	{
604	.vendor = PCI_VENDOR_ID_INTEL,
605	.device = 0x24d3, /* 82801EB ICH5 */
606	.subvendor = PCI_ANY_ID,
607	.subdevice = PCI_ANY_ID,
608	},
609	{
610	.vendor = PCI_VENDOR_ID_INTEL,
611	.device = 0x25a4, /* PCI_DEVICE_ID_INTEL_ESB_4 */
612	.subvendor = PCI_ANY_ID,
613	.subdevice = PCI_ANY_ID,
614	},
615	{
616	.vendor = PCI_VENDOR_ID_INTEL,
617	.device = 0x266a, /* PCI_DEVICE_ID_INTEL_ICH6_16 */
618	.subvendor = PCI_ANY_ID,
619	.subdevice = PCI_ANY_ID,
620	},
621	{ 0, }
622	};
623
624	static int __devinit i801_probe(struct pci_dev dev, const struct pci_device_id id)
625	{
626
627	if (i801_setup(dev)) {
628	dev_warn(dev,
629	"I801 not detected, module not inserted.\n");
630	return -ENODEV;
631	}
632
633	snprintf(i801_adapter.name, 32,
634	"SMBus I801 adapter at %04x", i801_smba);
635	return i2c_add_adapter(&i801_adapter);
636	}
637
638	static void __devexit i801_remove(struct pci_dev *dev)
639	{
640	i2c_del_adapter(&i801_adapter);
641	release_region(i801_smba, (isich4 ? 16 : 8));
642	}
643
644	static struct pci_driver i801_driver = {
645	.name = "i801 smbus",
646	.id_table = i801_ids,
647	.probe = i801_probe,
648	.remove = __devexit_p(i801_remove),
649	};
650
651	static int __init i2c_i801_init(void)
652	{
653	printk(KERN_INFO "i2c-i801 version %s (%s)\n", LM_VERSION, LM_DATE);
654	return pci_module_init(&i801_driver);
655	}
656
657	static void __exit i2c_i801_exit(void)
658	{
659	pci_unregister_driver(&i801_driver);
660	}
661
662	MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
663	"Philip Edelbrock <phil@netroedge.com>, "
664	"and Mark D. Studebaker <mdsxyz123@yahoo.com>");
665	MODULE_DESCRIPTION("I801 SMBus driver");
666	MODULE_LICENSE("GPL");
667
668	module_init(i2c_i801_init);
669	module_exit(i2c_i801_exit);

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