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i2c-i801.c @ 1773

Revision 1773, 16.5 KB (checked in by khali, 10 years ago)

Added missing device IDs, required for compiling with Linux kernel

2.4.18 and previous (VIA_8233A and INTEL_82801DB_3).

Property svn:eol-style set to native
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1	/*
2	i801.c - Part of lm_sensors, Linux kernel modules for hardware
3	monitoring
4	Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5	Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
6	<mdsxyz123@yahoo.com>
7
8	This program is free software; you can redistribute it and/or modify
9	it under the terms of the GNU General Public License as published by
10	the Free Software Foundation; either version 2 of the License, or
11	(at your option) any later version.
12
13	This program is distributed in the hope that it will be useful,
14	but WITHOUT ANY WARRANTY; without even the implied warranty of
15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	GNU General Public License for more details.
17
18	You should have received a copy of the GNU General Public License
19	along with this program; if not, write to the Free Software
20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21	*/
22
23	/*
24	SUPPORTED DEVICES PCI ID
25	82801AA 2413
26	82801AB 2423
27	82801BA 2443
28	82801CA/CAM 2483
29	82801DB 24C3 (HW PEC supported, 32 byte buffer not supported)
30
31	This driver supports several versions of Intel's I/O Controller Hubs (ICH).
32	For SMBus support, they are similar to the PIIX4 and are part
33	of Intel's '810' and other chipsets.
34	See the doc/busses/i2c-i801 file for details.
35	I2C Block Read and Process Call are not supported.
36	*/
37
38	/* Note: we assume there can only be one I801, with one SMBus interface */
39
40	/* #define DEBUG 1 */
41
42	#include <linux/module.h>
43	#include <linux/pci.h>
44	#include <linux/kernel.h>
45	#include <linux/stddef.h>
46	#include <linux/sched.h>
47	#include <linux/ioport.h>
48	#include <linux/init.h>
49	#include <linux/i2c.h>
50	#include <asm/io.h>
51	#include "version.h"
52	#include "sensors_compat.h"
53
54	/* 82801DB is undefined before kernel 2.4.19 */
55	#ifndef PCI_DEVICE_ID_INTEL_82801DB_3
56	#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3
57	#endif
58
59	#ifdef I2C_FUNC_SMBUS_BLOCK_DATA_PEC
60	#define HAVE_PEC
61	#endif
62
63	/* I801 SMBus address offsets */
64	#define SMBHSTSTS (0 + i801_smba)
65	#define SMBHSTCNT (2 + i801_smba)
66	#define SMBHSTCMD (3 + i801_smba)
67	#define SMBHSTADD (4 + i801_smba)
68	#define SMBHSTDAT0 (5 + i801_smba)
69	#define SMBHSTDAT1 (6 + i801_smba)
70	#define SMBBLKDAT (7 + i801_smba)
71	#define SMBPEC (8 + i801_smba) /* ICH4 only */
72	#define SMBAUXSTS (12 + i801_smba) /* ICH4 only */
73	#define SMBAUXCTL (13 + i801_smba) /* ICH4 only */
74
75	/* PCI Address Constants */
76	#define SMBBA 0x020
77	#define SMBHSTCFG 0x040
78	#define SMBREV 0x008
79
80	/* Host configuration bits for SMBHSTCFG */
81	#define SMBHSTCFG_HST_EN 1
82	#define SMBHSTCFG_SMB_SMI_EN 2
83	#define SMBHSTCFG_I2C_EN 4
84
85	/* Other settings */
86	#define MAX_TIMEOUT 100
87	#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
88
89	/* I801 command constants */
90	#define I801_QUICK 0x00
91	#define I801_BYTE 0x04
92	#define I801_BYTE_DATA 0x08
93	#define I801_WORD_DATA 0x0C
94	#define I801_PROC_CALL 0x10 /* later chips only, unimplemented */
95	#define I801_BLOCK_DATA 0x14
96	#define I801_I2C_BLOCK_DATA 0x18 /* unimplemented */
97	#define I801_BLOCK_LAST 0x34
98	#define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */
99	#define I801_START 0x40
100	#define I801_PEC_EN 0x80 /* ICH4 only */
101
102	/* insmod parameters */
103
104	/* If force_addr is set to anything different from 0, we forcibly enable
105	the I801 at the given address. VERY DANGEROUS! */
106	static int force_addr = 0;
107	MODULE_PARM(force_addr, "i");
108	MODULE_PARM_DESC(force_addr,
109	"Forcibly enable the I801 at the given address. "
110	"EXTREMELY DANGEROUS!");
111
112	static void i801_do_pause(unsigned int amount);
113	static int i801_transaction(void);
114	static int i801_block_transaction(union i2c_smbus_data *data,
115	char read_write, int command);
116
117	static unsigned short i801_smba;
118	static struct pci_dev *I801_dev;
119	static int isich4;
120
121	static int i801_setup(struct pci_dev *dev)
122	{
123	int error_return = 0;
124	unsigned char temp;
125
126	/* Note: we keep on searching until we have found 'function 3' */
127	if(PCI_FUNC(dev->devfn) != 3)
128	return -ENODEV;
129
130	I801_dev = dev;
131	if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_3)
132	isich4 = 1;
133	else
134	isich4 = 0;
135
136	/* Determine the address of the SMBus areas */
137	if (force_addr) {
138	i801_smba = force_addr & 0xfff0;
139	} else {
140	pci_read_config_word(I801_dev, SMBBA, &i801_smba);
141	i801_smba &= 0xfff0;
142	if(i801_smba == 0) {
143	dev_err(dev, "SMB base address uninitialized"
144	"- upgrade BIOS or use force_addr=0xaddr\n");
145	return -ENODEV;
146	}
147	}
148
149	if (!request_region(i801_smba, (isich4 ? 16 : 8), "i801-smbus")) {
150	dev_err(dev, "I801_smb region 0x%x already in use!\n",
151	i801_smba);
152	error_return = -EBUSY;
153	goto END;
154	}
155
156	pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
157	temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
158	pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
159
160	/* If force_addr is set, we program the new address here. Just to make
161	sure, we disable the device first. */
162	if (force_addr) {
163	pci_write_config_byte(I801_dev, SMBHSTCFG, temp & 0xfe);
164	pci_write_config_word(I801_dev, SMBBA, i801_smba);
165	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 0x01);
166	dev_warn(dev, "WARNING: I801 SMBus interface set to "
167	"new address %04x!\n", i801_smba);
168	} else if ((temp & 1) == 0) {
169	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 1);
170	dev_warn(dev, "enabling SMBus device\n");
171	}
172
173	if (temp & 0x02)
174	dev_dbg(dev, "I801 using Interrupt SMI# for SMBus.\n");
175	else
176	dev_dbg(dev, "I801 using PCI Interrupt for SMBus.\n");
177
178	pci_read_config_byte(I801_dev, SMBREV, &temp);
179	dev_dbg(dev, "SMBREV = 0x%X\n", temp);
180	dev_dbg(dev, "I801_smba = 0x%X\n", i801_smba);
181
182	END:
183	return error_return;
184	}
185
186
187	static void i801_do_pause(unsigned int amount)
188	{
189	current->state = TASK_INTERRUPTIBLE;
190	schedule_timeout(amount);
191	}
192
193	static int i801_transaction(void)
194	{
195	int temp;
196	int result = 0;
197	int timeout = 0;
198
199	dev_dbg(I801_dev, "Transaction (pre): CNT=%02x, CMD=%02x,"
200	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
201	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
202	inb_p(SMBHSTDAT1));
203
204	/* Make sure the SMBus host is ready to start transmitting */
205	/* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
206	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
207	dev_dbg(I801_dev, "SMBus busy (%02x). Resetting... \n",
208	temp);
209	outb_p(temp, SMBHSTSTS);
210	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
211	dev_dbg(I801_dev, "Failed! (%02x)\n", temp);
212	return -1;
213	} else {
214	dev_dbg(I801_dev, "Successfull!\n");
215	}
216	}
217
218	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
219
220	/* We will always wait for a fraction of a second! */
221	do {
222	i801_do_pause(1);
223	temp = inb_p(SMBHSTSTS);
224	} while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
225
226	/* If the SMBus is still busy, we give up */
227	if (timeout >= MAX_TIMEOUT) {
228	dev_dbg(I801_dev, "SMBus Timeout!\n");
229	result = -1;
230	}
231
232	if (temp & 0x10) {
233	result = -1;
234	dev_dbg(I801_dev, "Error: Failed bus transaction\n");
235	}
236
237	if (temp & 0x08) {
238	result = -1;
239	dev_err(I801_dev, "Bus collision! SMBus may be locked "
240	"until next hard reset. (sorry!)\n");
241	/* Clock stops and slave is stuck in mid-transmission */
242	}
243
244	if (temp & 0x04) {
245	result = -1;
246	dev_dbg(I801_dev, "Error: no response!\n");
247	}
248
249	if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
250	outb_p(inb(SMBHSTSTS), SMBHSTSTS);
251
252	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
253	dev_dbg(I801_dev, "Failed reset at end of transaction"
254	"(%02x)\n", temp);
255	}
256	dev_dbg(I801_dev, "Transaction (post): CNT=%02x, CMD=%02x, "
257	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
258	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
259	inb_p(SMBHSTDAT1));
260	return result;
261	}
262
263	/* All-inclusive block transaction function */
264	static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
265	int command)
266	{
267	int i, len;
268	int smbcmd;
269	int temp;
270	int result = 0;
271	int timeout;
272	unsigned char hostc, errmask;
273
274	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
275	if (read_write == I2C_SMBUS_WRITE) {
276	/* set I2C_EN bit in configuration register */
277	pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
278	pci_write_config_byte(I801_dev, SMBHSTCFG,
279	hostc \| SMBHSTCFG_I2C_EN);
280	} else {
281	dev_err(I801_dev,
282	"I2C_SMBUS_I2C_BLOCK_READ not DB!\n");
283	return -1;
284	}
285	}
286
287	if (read_write == I2C_SMBUS_WRITE) {
288	len = data->block[0];
289	if (len < 1)
290	len = 1;
291	if (len > 32)
292	len = 32;
293	outb_p(len, SMBHSTDAT0);
294	outb_p(data->block[1], SMBBLKDAT);
295	} else {
296	len = 32; /* max for reads */
297	}
298
299	if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
300	/* set 32 byte buffer */
301	}
302
303	for (i = 1; i <= len; i++) {
304	if (i == len && read_write == I2C_SMBUS_READ)
305	smbcmd = I801_BLOCK_LAST;
306	else
307	smbcmd = I801_BLOCK_DATA;
308	outb_p(smbcmd \| ENABLE_INT9, SMBHSTCNT);
309
310	dev_dbg(I801_dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
311	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
312	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
313	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
314
315	/* Make sure the SMBus host is ready to start transmitting */
316	temp = inb_p(SMBHSTSTS);
317	if (i == 1) {
318	/* Erronenous conditions before transaction:
319	* Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
320	errmask=0x9f;
321	} else {
322	/* Erronenous conditions during transaction:
323	* Failed, Bus_Err, Dev_Err, Intr */
324	errmask=0x1e;
325	}
326	if (temp & errmask) {
327	dev_dbg(I801_dev, "SMBus busy (%02x). "
328	"Resetting... \n", temp);
329	outb_p(temp, SMBHSTSTS);
330	if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
331	dev_err(I801_dev,
332	"Reset failed! (%02x)\n", temp);
333	result = -1;
334	goto END;
335	}
336	if (i != 1) {
337	/* if die in middle of block transaction, fail */
338	result = -1;
339	goto END;
340	}
341	}
342
343	if (i == 1)
344	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
345
346	/* We will always wait for a fraction of a second! */
347	timeout = 0;
348	do {
349	temp = inb_p(SMBHSTSTS);
350	i801_do_pause(1);
351	}
352	while ((!(temp & 0x80))
353	&& (timeout++ < MAX_TIMEOUT));
354
355	/* If the SMBus is still busy, we give up */
356	if (timeout >= MAX_TIMEOUT) {
357	result = -1;
358	dev_dbg(I801_dev, "SMBus Timeout!\n");
359	}
360
361	if (temp & 0x10) {
362	result = -1;
363	dev_dbg(I801_dev,
364	"Error: Failed bus transaction\n");
365	} else if (temp & 0x08) {
366	result = -1;
367	dev_err(I801_dev, "Bus collision!\n");
368	} else if (temp & 0x04) {
369	result = -1;
370	dev_dbg(I801_dev, "Error: no response!\n");
371	}
372
373	if (i == 1 && read_write == I2C_SMBUS_READ) {
374	len = inb_p(SMBHSTDAT0);
375	if (len < 1)
376	len = 1;
377	if (len > 32)
378	len = 32;
379	data->block[0] = len;
380	}
381
382	/* Retrieve/store value in SMBBLKDAT */
383	if (read_write == I2C_SMBUS_READ)
384	data->block[i] = inb_p(SMBBLKDAT);
385	if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
386	outb_p(data->block[i+1], SMBBLKDAT);
387	if ((temp & 0x9e) != 0x00)
388	outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
389
390	if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
391	dev_dbg(I801_dev,
392	"Bad status (%02x) at end of transaction\n",
393	temp);
394	}
395	dev_dbg(I801_dev, "Block (post %d): CNT=%02x, CMD=%02x, "
396	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
397	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
398	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
399
400	if (result < 0)
401	goto END;
402	}
403
404	#ifdef HAVE_PEC
405	if(isich4 && command == I2C_SMBUS_BLOCK_DATA_PEC) {
406	/* wait for INTR bit as advised by Intel */
407	timeout = 0;
408	do {
409	temp = inb_p(SMBHSTSTS);
410	i801_do_pause(1);
411	} while ((!(temp & 0x02))
412	&& (timeout++ < MAX_TIMEOUT));
413
414	if (timeout >= MAX_TIMEOUT) {
415	dev_dbg(I801_dev, "PEC Timeout!\n");
416	}
417	outb_p(temp, SMBHSTSTS);
418	}
419	#endif
420	result = 0;
421	END:
422	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
423	/* restore saved configuration register value */
424	pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
425	}
426	return result;
427	}
428
429	/* Return -1 on error. */
430	static s32 i801_access(struct i2c_adapter * adap, u16 addr,
431	unsigned short flags, char read_write, u8 command,
432	int size, union i2c_smbus_data * data)
433	{
434	int hwpec = 0;
435	int block = 0;
436	int ret, xact = 0;
437
438	#ifdef HAVE_PEC
439	if(isich4)
440	hwpec = (flags & I2C_CLIENT_PEC) != 0;
441	#endif
442
443	switch (size) {
444	case I2C_SMBUS_QUICK:
445	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
446	SMBHSTADD);
447	xact = I801_QUICK;
448	break;
449	case I2C_SMBUS_BYTE:
450	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
451	SMBHSTADD);
452	if (read_write == I2C_SMBUS_WRITE)
453	outb_p(command, SMBHSTCMD);
454	xact = I801_BYTE;
455	break;
456	case I2C_SMBUS_BYTE_DATA:
457	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
458	SMBHSTADD);
459	outb_p(command, SMBHSTCMD);
460	if (read_write == I2C_SMBUS_WRITE)
461	outb_p(data->byte, SMBHSTDAT0);
462	xact = I801_BYTE_DATA;
463	break;
464	case I2C_SMBUS_WORD_DATA:
465	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
466	SMBHSTADD);
467	outb_p(command, SMBHSTCMD);
468	if (read_write == I2C_SMBUS_WRITE) {
469	outb_p(data->word & 0xff, SMBHSTDAT0);
470	outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
471	}
472	xact = I801_WORD_DATA;
473	break;
474	case I2C_SMBUS_BLOCK_DATA:
475	case I2C_SMBUS_I2C_BLOCK_DATA:
476	#ifdef HAVE_PEC
477	case I2C_SMBUS_BLOCK_DATA_PEC:
478	if(hwpec && size == I2C_SMBUS_BLOCK_DATA)
479	size = I2C_SMBUS_BLOCK_DATA_PEC;
480	#endif
481	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
482	SMBHSTADD);
483	outb_p(command, SMBHSTCMD);
484	block = 1;
485	break;
486	case I2C_SMBUS_PROC_CALL:
487	default:
488	dev_err(I801_dev, "Unsupported transaction %d\n", size);
489	return -1;
490	}
491
492	#ifdef HAVE_PEC
493	if(isich4 && hwpec) {
494	if(size != I2C_SMBUS_QUICK &&
495	size != I2C_SMBUS_I2C_BLOCK_DATA)
496	outb_p(1, SMBAUXCTL); /* enable HW PEC */
497	}
498	#endif
499	if(block)
500	ret = i801_block_transaction(data, read_write, size);
501	else {
502	outb_p(xact \| ENABLE_INT9, SMBHSTCNT);
503	ret = i801_transaction();
504	}
505
506	#ifdef HAVE_PEC
507	if(isich4 && hwpec) {
508	if(size != I2C_SMBUS_QUICK &&
509	size != I2C_SMBUS_I2C_BLOCK_DATA)
510	outb_p(0, SMBAUXCTL);
511	}
512	#endif
513
514	if(block)
515	return ret;
516	if(ret)
517	return -1;
518	if ((read_write == I2C_SMBUS_WRITE) \|\| (xact == I801_QUICK))
519	return 0;
520
521	switch (xact & 0x7f) {
522	case I801_BYTE: /* Result put in SMBHSTDAT0 */
523	case I801_BYTE_DATA:
524	data->byte = inb_p(SMBHSTDAT0);
525	break;
526	case I801_WORD_DATA:
527	data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
528	break;
529	}
530	return 0;
531	}
532
533
534	static u32 i801_func(struct i2c_adapter *adapter)
535	{
536	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
537	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
538	I2C_FUNC_SMBUS_BLOCK_DATA \| I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
539	#ifdef HAVE_PEC
540	\| (isich4 ? I2C_FUNC_SMBUS_BLOCK_DATA_PEC \|
541	I2C_FUNC_SMBUS_HWPEC_CALC
542	: 0)
543	#endif
544	;
545	}
546
547	static struct i2c_algorithm smbus_algorithm = {
548	.name = "Non-I2C SMBus adapter",
549	.id = I2C_ALGO_SMBUS,
550	.smbus_xfer = i801_access,
551	.functionality = i801_func,
552	};
553
554	static struct i2c_adapter i801_adapter = {
555	.owner = THIS_MODULE,
556	.id = I2C_ALGO_SMBUS \| I2C_HW_SMBUS_I801,
557	.algo = &smbus_algorithm,
558	.name = "unset",
559	};
560
561	static struct pci_device_id i801_ids[] __devinitdata = {
562	{
563	.vendor = PCI_VENDOR_ID_INTEL,
564	.device = PCI_DEVICE_ID_INTEL_82801AA_3,
565	.subvendor = PCI_ANY_ID,
566	.subdevice = PCI_ANY_ID,
567	},
568	{
569	.vendor = PCI_VENDOR_ID_INTEL,
570	.device = PCI_DEVICE_ID_INTEL_82801AB_3,
571	.subvendor = PCI_ANY_ID,
572	.subdevice = PCI_ANY_ID,
573	},
574	{
575	.vendor = PCI_VENDOR_ID_INTEL,
576	.device = PCI_DEVICE_ID_INTEL_82801BA_2,
577	.subvendor = PCI_ANY_ID,
578	.subdevice = PCI_ANY_ID,
579	},
580	{
581	.vendor = PCI_VENDOR_ID_INTEL,
582	.device = PCI_DEVICE_ID_INTEL_82801CA_3,
583	.subvendor = PCI_ANY_ID,
584	.subdevice = PCI_ANY_ID,
585	},
586	{
587	.vendor = PCI_VENDOR_ID_INTEL,
588	.device = PCI_DEVICE_ID_INTEL_82801DB_3,
589	.subvendor = PCI_ANY_ID,
590	.subdevice = PCI_ANY_ID,
591	},
592	{ 0, }
593	};
594
595	static int __devinit i801_probe(struct pci_dev dev, const struct pci_device_id id)
596	{
597
598	if (i801_setup(dev)) {
599	dev_warn(dev,
600	"I801 not detected, module not inserted.\n");
601	return -ENODEV;
602	}
603
604	snprintf(i801_adapter.name, 32,
605	"SMBus I801 adapter at %04x", i801_smba);
606	return i2c_add_adapter(&i801_adapter);
607	}
608
609	static void __devexit i801_remove(struct pci_dev *dev)
610	{
611	i2c_del_adapter(&i801_adapter);
612	}
613
614	static struct pci_driver i801_driver = {
615	.name = "i801 smbus",
616	.id_table = i801_ids,
617	.probe = i801_probe,
618	.remove = __devexit_p(i801_remove),
619	};
620
621	static int __init i2c_i801_init(void)
622	{
623	printk(KERN_INFO "i2c-i801 version %s (%s)\n", LM_VERSION, LM_DATE);
624	return pci_module_init(&i801_driver);
625	}
626
627	static void __exit i2c_i801_exit(void)
628	{
629	pci_unregister_driver(&i801_driver);
630	release_region(i801_smba, (isich4 ? 16 : 8));
631	}
632
633	MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
634	"Philip Edelbrock <phil@netroedge.com>, "
635	"and Mark D. Studebaker <mdsxyz123@yahoo.com>");
636	MODULE_DESCRIPTION("I801 SMBus driver");
637	MODULE_LICENSE("GPL");
638
639	module_init(i2c_i801_init);
640	module_exit(i2c_i801_exit);

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