Context Navigation

i2c-i801.c @ 1763

Revision 1763, 16.3 KB (checked in by mds, 10 years ago)
backport from kernel 2.5.69. untested.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`

Line
1	/*
2	i801.c - Part of lm_sensors, Linux kernel modules for hardware
3	monitoring
4	Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5	Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
6	<mdsxyz123@yahoo.com>
7
8	This program is free software; you can redistribute it and/or modify
9	it under the terms of the GNU General Public License as published by
10	the Free Software Foundation; either version 2 of the License, or
11	(at your option) any later version.
12
13	This program is distributed in the hope that it will be useful,
14	but WITHOUT ANY WARRANTY; without even the implied warranty of
15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	GNU General Public License for more details.
17
18	You should have received a copy of the GNU General Public License
19	along with this program; if not, write to the Free Software
20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21	*/
22
23	/*
24	SUPPORTED DEVICES PCI ID
25	82801AA 2413
26	82801AB 2423
27	82801BA 2443
28	82801CA/CAM 2483
29	82801DB 24C3 (HW PEC supported, 32 byte buffer not supported)
30
31	This driver supports several versions of Intel's I/O Controller Hubs (ICH).
32	For SMBus support, they are similar to the PIIX4 and are part
33	of Intel's '810' and other chipsets.
34	See the doc/busses/i2c-i801 file for details.
35	I2C Block Read and Process Call are not supported.
36	*/
37
38	/* Note: we assume there can only be one I801, with one SMBus interface */
39
40	/* #define DEBUG 1 */
41
42	#include <linux/module.h>
43	#include <linux/pci.h>
44	#include <linux/kernel.h>
45	#include <linux/stddef.h>
46	#include <linux/sched.h>
47	#include <linux/ioport.h>
48	#include <linux/init.h>
49	#include <linux/i2c.h>
50	#include <asm/io.h>
51	#include "version.h"
52	#include "sensors_compat.h"
53
54	#ifdef I2C_FUNC_SMBUS_BLOCK_DATA_PEC
55	#define HAVE_PEC
56	#endif
57
58	/* I801 SMBus address offsets */
59	#define SMBHSTSTS (0 + i801_smba)
60	#define SMBHSTCNT (2 + i801_smba)
61	#define SMBHSTCMD (3 + i801_smba)
62	#define SMBHSTADD (4 + i801_smba)
63	#define SMBHSTDAT0 (5 + i801_smba)
64	#define SMBHSTDAT1 (6 + i801_smba)
65	#define SMBBLKDAT (7 + i801_smba)
66	#define SMBPEC (8 + i801_smba) /* ICH4 only */
67	#define SMBAUXSTS (12 + i801_smba) /* ICH4 only */
68	#define SMBAUXCTL (13 + i801_smba) /* ICH4 only */
69
70	/* PCI Address Constants */
71	#define SMBBA 0x020
72	#define SMBHSTCFG 0x040
73	#define SMBREV 0x008
74
75	/* Host configuration bits for SMBHSTCFG */
76	#define SMBHSTCFG_HST_EN 1
77	#define SMBHSTCFG_SMB_SMI_EN 2
78	#define SMBHSTCFG_I2C_EN 4
79
80	/* Other settings */
81	#define MAX_TIMEOUT 100
82	#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
83
84	/* I801 command constants */
85	#define I801_QUICK 0x00
86	#define I801_BYTE 0x04
87	#define I801_BYTE_DATA 0x08
88	#define I801_WORD_DATA 0x0C
89	#define I801_PROC_CALL 0x10 /* later chips only, unimplemented */
90	#define I801_BLOCK_DATA 0x14
91	#define I801_I2C_BLOCK_DATA 0x18 /* unimplemented */
92	#define I801_BLOCK_LAST 0x34
93	#define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */
94	#define I801_START 0x40
95	#define I801_PEC_EN 0x80 /* ICH4 only */
96
97	/* insmod parameters */
98
99	/* If force_addr is set to anything different from 0, we forcibly enable
100	the I801 at the given address. VERY DANGEROUS! */
101	static int force_addr = 0;
102	MODULE_PARM(force_addr, "i");
103	MODULE_PARM_DESC(force_addr,
104	"Forcibly enable the I801 at the given address. "
105	"EXTREMELY DANGEROUS!");
106
107	static void i801_do_pause(unsigned int amount);
108	static int i801_transaction(void);
109	static int i801_block_transaction(union i2c_smbus_data *data,
110	char read_write, int command);
111
112	static unsigned short i801_smba;
113	static struct pci_dev *I801_dev;
114	static int isich4;
115
116	static int i801_setup(struct pci_dev *dev)
117	{
118	int error_return = 0;
119	unsigned char temp;
120
121	/* Note: we keep on searching until we have found 'function 3' */
122	if(PCI_FUNC(dev->devfn) != 3)
123	return -ENODEV;
124
125	I801_dev = dev;
126	if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_3)
127	isich4 = 1;
128	else
129	isich4 = 0;
130
131	/* Determine the address of the SMBus areas */
132	if (force_addr) {
133	i801_smba = force_addr & 0xfff0;
134	} else {
135	pci_read_config_word(I801_dev, SMBBA, &i801_smba);
136	i801_smba &= 0xfff0;
137	if(i801_smba == 0) {
138	dev_err(dev, "SMB base address uninitialized"
139	"- upgrade BIOS or use force_addr=0xaddr\n");
140	return -ENODEV;
141	}
142	}
143
144	if (!request_region(i801_smba, (isich4 ? 16 : 8), "i801-smbus")) {
145	dev_err(dev, "I801_smb region 0x%x already in use!\n",
146	i801_smba);
147	error_return = -EBUSY;
148	goto END;
149	}
150
151	pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
152	temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
153	pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
154
155	/* If force_addr is set, we program the new address here. Just to make
156	sure, we disable the device first. */
157	if (force_addr) {
158	pci_write_config_byte(I801_dev, SMBHSTCFG, temp & 0xfe);
159	pci_write_config_word(I801_dev, SMBBA, i801_smba);
160	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 0x01);
161	dev_warn(dev, "WARNING: I801 SMBus interface set to "
162	"new address %04x!\n", i801_smba);
163	} else if ((temp & 1) == 0) {
164	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 1);
165	dev_warn(dev, "enabling SMBus device\n");
166	}
167
168	if (temp & 0x02)
169	dev_dbg(dev, "I801 using Interrupt SMI# for SMBus.\n");
170	else
171	dev_dbg(dev, "I801 using PCI Interrupt for SMBus.\n");
172
173	pci_read_config_byte(I801_dev, SMBREV, &temp);
174	dev_dbg(dev, "SMBREV = 0x%X\n", temp);
175	dev_dbg(dev, "I801_smba = 0x%X\n", i801_smba);
176
177	END:
178	return error_return;
179	}
180
181
182	static void i801_do_pause(unsigned int amount)
183	{
184	current->state = TASK_INTERRUPTIBLE;
185	schedule_timeout(amount);
186	}
187
188	static int i801_transaction(void)
189	{
190	int temp;
191	int result = 0;
192	int timeout = 0;
193
194	dev_dbg(I801_dev, "Transaction (pre): CNT=%02x, CMD=%02x,"
195	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
196	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
197	inb_p(SMBHSTDAT1));
198
199	/* Make sure the SMBus host is ready to start transmitting */
200	/* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
201	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
202	dev_dbg(I801_dev, "SMBus busy (%02x). Resetting... \n",
203	temp);
204	outb_p(temp, SMBHSTSTS);
205	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
206	dev_dbg(I801_dev, "Failed! (%02x)\n", temp);
207	return -1;
208	} else {
209	dev_dbg(I801_dev, "Successfull!\n");
210	}
211	}
212
213	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
214
215	/* We will always wait for a fraction of a second! */
216	do {
217	i801_do_pause(1);
218	temp = inb_p(SMBHSTSTS);
219	} while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
220
221	/* If the SMBus is still busy, we give up */
222	if (timeout >= MAX_TIMEOUT) {
223	dev_dbg(I801_dev, "SMBus Timeout!\n");
224	result = -1;
225	}
226
227	if (temp & 0x10) {
228	result = -1;
229	dev_dbg(I801_dev, "Error: Failed bus transaction\n");
230	}
231
232	if (temp & 0x08) {
233	result = -1;
234	dev_err(I801_dev, "Bus collision! SMBus may be locked "
235	"until next hard reset. (sorry!)\n");
236	/* Clock stops and slave is stuck in mid-transmission */
237	}
238
239	if (temp & 0x04) {
240	result = -1;
241	dev_dbg(I801_dev, "Error: no response!\n");
242	}
243
244	if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
245	outb_p(inb(SMBHSTSTS), SMBHSTSTS);
246
247	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
248	dev_dbg(I801_dev, "Failed reset at end of transaction"
249	"(%02x)\n", temp);
250	}
251	dev_dbg(I801_dev, "Transaction (post): CNT=%02x, CMD=%02x, "
252	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
253	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
254	inb_p(SMBHSTDAT1));
255	return result;
256	}
257
258	/* All-inclusive block transaction function */
259	static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
260	int command)
261	{
262	int i, len;
263	int smbcmd;
264	int temp;
265	int result = 0;
266	int timeout;
267	unsigned char hostc, errmask;
268
269	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
270	if (read_write == I2C_SMBUS_WRITE) {
271	/* set I2C_EN bit in configuration register */
272	pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
273	pci_write_config_byte(I801_dev, SMBHSTCFG,
274	hostc \| SMBHSTCFG_I2C_EN);
275	} else {
276	dev_err(I801_dev,
277	"I2C_SMBUS_I2C_BLOCK_READ not DB!\n");
278	return -1;
279	}
280	}
281
282	if (read_write == I2C_SMBUS_WRITE) {
283	len = data->block[0];
284	if (len < 1)
285	len = 1;
286	if (len > 32)
287	len = 32;
288	outb_p(len, SMBHSTDAT0);
289	outb_p(data->block[1], SMBBLKDAT);
290	} else {
291	len = 32; /* max for reads */
292	}
293
294	if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
295	/* set 32 byte buffer */
296	}
297
298	for (i = 1; i <= len; i++) {
299	if (i == len && read_write == I2C_SMBUS_READ)
300	smbcmd = I801_BLOCK_LAST;
301	else
302	smbcmd = I801_BLOCK_DATA;
303	outb_p(smbcmd \| ENABLE_INT9, SMBHSTCNT);
304
305	dev_dbg(I801_dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
306	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
307	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
308	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
309
310	/* Make sure the SMBus host is ready to start transmitting */
311	temp = inb_p(SMBHSTSTS);
312	if (i == 1) {
313	/* Erronenous conditions before transaction:
314	* Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
315	errmask=0x9f;
316	} else {
317	/* Erronenous conditions during transaction:
318	* Failed, Bus_Err, Dev_Err, Intr */
319	errmask=0x1e;
320	}
321	if (temp & errmask) {
322	dev_dbg(I801_dev, "SMBus busy (%02x). "
323	"Resetting... \n", temp);
324	outb_p(temp, SMBHSTSTS);
325	if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
326	dev_err(I801_dev,
327	"Reset failed! (%02x)\n", temp);
328	result = -1;
329	goto END;
330	}
331	if (i != 1) {
332	/* if die in middle of block transaction, fail */
333	result = -1;
334	goto END;
335	}
336	}
337
338	if (i == 1)
339	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
340
341	/* We will always wait for a fraction of a second! */
342	timeout = 0;
343	do {
344	temp = inb_p(SMBHSTSTS);
345	i801_do_pause(1);
346	}
347	while ((!(temp & 0x80))
348	&& (timeout++ < MAX_TIMEOUT));
349
350	/* If the SMBus is still busy, we give up */
351	if (timeout >= MAX_TIMEOUT) {
352	result = -1;
353	dev_dbg(I801_dev, "SMBus Timeout!\n");
354	}
355
356	if (temp & 0x10) {
357	result = -1;
358	dev_dbg(I801_dev,
359	"Error: Failed bus transaction\n");
360	} else if (temp & 0x08) {
361	result = -1;
362	dev_err(I801_dev, "Bus collision!\n");
363	} else if (temp & 0x04) {
364	result = -1;
365	dev_dbg(I801_dev, "Error: no response!\n");
366	}
367
368	if (i == 1 && read_write == I2C_SMBUS_READ) {
369	len = inb_p(SMBHSTDAT0);
370	if (len < 1)
371	len = 1;
372	if (len > 32)
373	len = 32;
374	data->block[0] = len;
375	}
376
377	/* Retrieve/store value in SMBBLKDAT */
378	if (read_write == I2C_SMBUS_READ)
379	data->block[i] = inb_p(SMBBLKDAT);
380	if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
381	outb_p(data->block[i+1], SMBBLKDAT);
382	if ((temp & 0x9e) != 0x00)
383	outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
384
385	if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
386	dev_dbg(I801_dev,
387	"Bad status (%02x) at end of transaction\n",
388	temp);
389	}
390	dev_dbg(I801_dev, "Block (post %d): CNT=%02x, CMD=%02x, "
391	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
392	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
393	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
394
395	if (result < 0)
396	goto END;
397	}
398
399	#ifdef HAVE_PEC
400	if(isich4 && command == I2C_SMBUS_BLOCK_DATA_PEC) {
401	/* wait for INTR bit as advised by Intel */
402	timeout = 0;
403	do {
404	temp = inb_p(SMBHSTSTS);
405	i801_do_pause(1);
406	} while ((!(temp & 0x02))
407	&& (timeout++ < MAX_TIMEOUT));
408
409	if (timeout >= MAX_TIMEOUT) {
410	dev_dbg(I801_dev, "PEC Timeout!\n");
411	}
412	outb_p(temp, SMBHSTSTS);
413	}
414	#endif
415	result = 0;
416	END:
417	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
418	/* restore saved configuration register value */
419	pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
420	}
421	return result;
422	}
423
424	/* Return -1 on error. */
425	static s32 i801_access(struct i2c_adapter * adap, u16 addr,
426	unsigned short flags, char read_write, u8 command,
427	int size, union i2c_smbus_data * data)
428	{
429	int hwpec = 0;
430	int block = 0;
431	int ret, xact = 0;
432
433	#ifdef HAVE_PEC
434	if(isich4)
435	hwpec = (flags & I2C_CLIENT_PEC) != 0;
436	#endif
437
438	switch (size) {
439	case I2C_SMBUS_QUICK:
440	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
441	SMBHSTADD);
442	xact = I801_QUICK;
443	break;
444	case I2C_SMBUS_BYTE:
445	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
446	SMBHSTADD);
447	if (read_write == I2C_SMBUS_WRITE)
448	outb_p(command, SMBHSTCMD);
449	xact = I801_BYTE;
450	break;
451	case I2C_SMBUS_BYTE_DATA:
452	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
453	SMBHSTADD);
454	outb_p(command, SMBHSTCMD);
455	if (read_write == I2C_SMBUS_WRITE)
456	outb_p(data->byte, SMBHSTDAT0);
457	xact = I801_BYTE_DATA;
458	break;
459	case I2C_SMBUS_WORD_DATA:
460	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
461	SMBHSTADD);
462	outb_p(command, SMBHSTCMD);
463	if (read_write == I2C_SMBUS_WRITE) {
464	outb_p(data->word & 0xff, SMBHSTDAT0);
465	outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
466	}
467	xact = I801_WORD_DATA;
468	break;
469	case I2C_SMBUS_BLOCK_DATA:
470	case I2C_SMBUS_I2C_BLOCK_DATA:
471	#ifdef HAVE_PEC
472	case I2C_SMBUS_BLOCK_DATA_PEC:
473	if(hwpec && size == I2C_SMBUS_BLOCK_DATA)
474	size = I2C_SMBUS_BLOCK_DATA_PEC;
475	#endif
476	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
477	SMBHSTADD);
478	outb_p(command, SMBHSTCMD);
479	block = 1;
480	break;
481	case I2C_SMBUS_PROC_CALL:
482	default:
483	dev_err(I801_dev, "Unsupported transaction %d\n", size);
484	return -1;
485	}
486
487	#ifdef HAVE_PEC
488	if(isich4 && hwpec) {
489	if(size != I2C_SMBUS_QUICK &&
490	size != I2C_SMBUS_I2C_BLOCK_DATA)
491	outb_p(1, SMBAUXCTL); /* enable HW PEC */
492	}
493	#endif
494	if(block)
495	ret = i801_block_transaction(data, read_write, size);
496	else {
497	outb_p(xact \| ENABLE_INT9, SMBHSTCNT);
498	ret = i801_transaction();
499	}
500
501	#ifdef HAVE_PEC
502	if(isich4 && hwpec) {
503	if(size != I2C_SMBUS_QUICK &&
504	size != I2C_SMBUS_I2C_BLOCK_DATA)
505	outb_p(0, SMBAUXCTL);
506	}
507	#endif
508
509	if(block)
510	return ret;
511	if(ret)
512	return -1;
513	if ((read_write == I2C_SMBUS_WRITE) \|\| (xact == I801_QUICK))
514	return 0;
515
516	switch (xact & 0x7f) {
517	case I801_BYTE: /* Result put in SMBHSTDAT0 */
518	case I801_BYTE_DATA:
519	data->byte = inb_p(SMBHSTDAT0);
520	break;
521	case I801_WORD_DATA:
522	data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
523	break;
524	}
525	return 0;
526	}
527
528
529	static u32 i801_func(struct i2c_adapter *adapter)
530	{
531	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
532	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
533	I2C_FUNC_SMBUS_BLOCK_DATA \| I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
534	#ifdef HAVE_PEC
535	\| (isich4 ? I2C_FUNC_SMBUS_BLOCK_DATA_PEC \|
536	I2C_FUNC_SMBUS_HWPEC_CALC
537	: 0)
538	#endif
539	;
540	}
541
542	static struct i2c_algorithm smbus_algorithm = {
543	.name = "Non-I2C SMBus adapter",
544	.id = I2C_ALGO_SMBUS,
545	.smbus_xfer = i801_access,
546	.functionality = i801_func,
547	};
548
549	static struct i2c_adapter i801_adapter = {
550	.owner = THIS_MODULE,
551	.id = I2C_ALGO_SMBUS \| I2C_HW_SMBUS_I801,
552	.algo = &smbus_algorithm,
553	.name = "unset",
554	};
555
556	static struct pci_device_id i801_ids[] __devinitdata = {
557	{
558	.vendor = PCI_VENDOR_ID_INTEL,
559	.device = PCI_DEVICE_ID_INTEL_82801AA_3,
560	.subvendor = PCI_ANY_ID,
561	.subdevice = PCI_ANY_ID,
562	},
563	{
564	.vendor = PCI_VENDOR_ID_INTEL,
565	.device = PCI_DEVICE_ID_INTEL_82801AB_3,
566	.subvendor = PCI_ANY_ID,
567	.subdevice = PCI_ANY_ID,
568	},
569	{
570	.vendor = PCI_VENDOR_ID_INTEL,
571	.device = PCI_DEVICE_ID_INTEL_82801BA_2,
572	.subvendor = PCI_ANY_ID,
573	.subdevice = PCI_ANY_ID,
574	},
575	{
576	.vendor = PCI_VENDOR_ID_INTEL,
577	.device = PCI_DEVICE_ID_INTEL_82801CA_3,
578	.subvendor = PCI_ANY_ID,
579	.subdevice = PCI_ANY_ID,
580	},
581	{
582	.vendor = PCI_VENDOR_ID_INTEL,
583	.device = PCI_DEVICE_ID_INTEL_82801DB_3,
584	.subvendor = PCI_ANY_ID,
585	.subdevice = PCI_ANY_ID,
586	},
587	{ 0, }
588	};
589
590	static int __devinit i801_probe(struct pci_dev dev, const struct pci_device_id id)
591	{
592
593	if (i801_setup(dev)) {
594	dev_warn(dev,
595	"I801 not detected, module not inserted.\n");
596	return -ENODEV;
597	}
598
599	snprintf(i801_adapter.name, 32,
600	"SMBus I801 adapter at %04x", i801_smba);
601	return i2c_add_adapter(&i801_adapter);
602	}
603
604	static void __devexit i801_remove(struct pci_dev *dev)
605	{
606	i2c_del_adapter(&i801_adapter);
607	}
608
609	static struct pci_driver i801_driver = {
610	.name = "i801 smbus",
611	.id_table = i801_ids,
612	.probe = i801_probe,
613	.remove = __devexit_p(i801_remove),
614	};
615
616	static int __init i2c_i801_init(void)
617	{
618	printk(KERN_INFO "i2c-i801 version %s (%s)\n", LM_VERSION, LM_DATE);
619	return pci_module_init(&i801_driver);
620	}
621
622	static void __exit i2c_i801_exit(void)
623	{
624	pci_unregister_driver(&i801_driver);
625	release_region(i801_smba, (isich4 ? 16 : 8));
626	}
627
628	MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
629	"Philip Edelbrock <phil@netroedge.com>, "
630	"and Mark D. Studebaker <mdsxyz123@yahoo.com>");
631	MODULE_DESCRIPTION("I801 SMBus driver");
632	MODULE_LICENSE("GPL");
633
634	module_init(i2c_i801_init);
635	module_exit(i2c_i801_exit);

Note: See TracBrowser for help on using the browser.

Context Navigation

root/lm-sensors/trunk/kernel/busses/i2c-i801.c @ 1763

Download in other formats: